Abstract
This paper proposes a triple time-to-digital converter (TDC) for a field-programmable gate array (FPGA) platform with dual operation modes. First, the proposed triple-TDC employs the real-time calibration circuit followed by the traditional tapped delay line architecture to improve the environmental effect for the application of multiple TDCs. Second, the triple modular redundancy scheme is used to deal with the uncertainty in the FPGA device for improving the linearity for the application of a single TDC. The proposed triple-TDC is implemented in a Xilinx Virtex-5 FPGA platform and has a time resolution of 40 ps root mean square for multi-mode operation. Moreover, the ranges of differential nonlinearity and integral nonlinearity can be improved by 56 % and 37 % , respectively, for single-mode operation.
Highlights
Time-to-digital converters (TDCs) are crucial components in scientific applications [1,2,3], such as positron emission tomography (PET) [4,5,6,7,8,9], time-of-flight (TOF) image sensors [9,10], and light detection and ranging (LiDAR) [11,12,13,14]
A constant-delay stop signal generated from the start signal is adapted in single-mode operation to measure the root mean square (RMS) of the triple-TDC with the triple modular redundancy (TMR) function
The measurement results indicate that the differential non-linearity (DNL) values of the triple-TDC were [−0.80, 0.84], [−0.99, 0.85], and [−0.92, 0.94]
Summary
Time-to-digital converters (TDCs) are crucial components in scientific applications [1,2,3], such as positron emission tomography (PET) [4,5,6,7,8,9], time-of-flight (TOF) image sensors [9,10], and light detection and ranging (LiDAR) [11,12,13,14]. Researchers have designed specific calibration circuits to deal with the issue of nonlinearity in FPGA-based TDCs. To improve the linearity in FPGA-based TDC design, Kalisz et al presented the calibration circuit to implement a TDC having a resolution of 200 ps and a measurement range of 43 ns in a QuickLogic pASIC FPGA device [18,19]. A dual-mode FPGA-based triple-TDC is proposed to deal with the environment effect and improve the time linearity. The triple modular redundancy (TMR) scheme [32] is used to improve the uncertainty in the FPGA device for single-mode operation, such as the UWB effect. The TMR triple-TDC can achieve a resolution of 35.5 ps RMS and improve INL and DNL values by an average of 56% and 37%, respectively
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Free) 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
