Abstract
Content-addressable memory (CAM) is a type of associative memory, which returns the address of a given search input in one clock cycle. Many designs are available to emulate the CAM functionality inside the re-configurable hardware, field-programmable gate arrays (FPGAs), using static random-access memory (SRAM) and flip-flops. FPGA-based CAMs are becoming popular due to the rapid growth in software defined networks (SDNs), which uses CAM for packet classification. Emulated designs of CAM consume much dynamic power owing to a high amount of switching activity and computation involved in finding the address of the search key. In this paper, we present a power and resource efficient binary CAM architecture, Zi-CAM, which consumes less power and uses fewer resources than the available architectures of SRAM-based CAM on FPGAs. Zi-CAM consists of two main blocks. RAM block (RB) is activated when there is a sequence of repeating zeros in the input search word; otherwise, lookup tables (LUT) block (LB) is activated. Zi-CAM is implemented on Xilinx Virtex-6 FPGA for the size 64 × 36 which improved power consumption and hardware cost by 30 and 32%, respectively, compared to the available FPGA-based CAMs.
Highlights
Field-programmable gate arrays (FPGAs) are becoming an increasingly favorable platform for systems implementation because of their hardware-like performance and software-like reconfigurability.Modern FPGAs provide a vast amount of configurable logic and embedded memory blocks operating at a high clock rate [1,2]
The update latency of Zi-content-addressable memory (CAM) is independent of the size of CAM while in other random-access memory (RAM)-based CAMs, it varies with the size of CAM
An 8 × 10 Zi-CAM consists of one Lookup tables block (LB), one RAM block (RB) (RAM of size 64 × 3), a 2:1 MUX and 6-bit AND/NAND gate which acts as Block Selector (BSel)
Summary
Field-programmable gate arrays (FPGAs) are becoming an increasingly favorable platform for systems implementation because of their hardware-like performance and software-like reconfigurability. In a CAM, every location is accessed by its content rather than by address which is considered to be similar to the behavior of a human brain [3,4] It returns the address of the input search word in one clock cycle. Conventional CAM (on ASIC) has the drawback of high power consumption, limited storage density, non-scalability, and high implementation cost [3,13], compared with a random-access memory (RAM). A binary CAM design based on distributed memory (LUTRAMs) with lower hardware cost as well as reduced power consumption is proposed and is successfully implemented on FPGA. We use the LUTRAMs and exploit its 6-input structure in modern FPGAs to save power consumption.
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