Write Error Rate Research Articles

Write error rate analysis of field-free spin-orbit torque switching in conically magnetized free layer nanomagnet

Enhancing the performance of magnetic random access memories (MRAMs) is crucial, considering speed, energy efficiency, and endurance. Spin-orbit torque-based MRAMs offer ultrafast operation and enhanced reliability. Still, the energy efficiency and external magnetic field requirement for deterministic switching of nanomagnets with perpendicular magnetic anisotropy (PMA) are a significant hurdle. To address these issues, one of the proposed solutions employs a conically magnetized free layer magnetic tunnel junction device featuring second-order PMA. This approach can minimize the required switching current density by leveraging the interplay between first- and second-order PMA energies. Additionally, coupling with exchange bias from the antiferromagnet can eliminate the need for an external field entirely. Our analysis investigates the impact of current density (magnitude and rise/fall time), first- and second-order PMA fields, exchange bias, and field-like torque on the device's switching performance. By optimizing the perpendicular magnetic anisotropies, we report improvement in the write error rate from 10−4 to 10−7. Our findings hold promise for magnetic memory applications.

Probability distribution of write failure in a memory cell array consisting of magnetic tunnel junction elements with distributed write error rates

Write failure (WF) is a major reliability issue for applications of magnetoresistive random access memory (MRAM), and much effort has been devoted to reducing the write error rate (WER), which is the probability of write failures of a memory cell. Recently, it was shown that the WER of MRAM obeys a skewed probability distribution even though the variation in material parameters obeys a normal distribution. However, little is known about the effect of WER distribution on WF in a memory cell array. Here, we study WF in a memory cell array consisting of magnetic tunnel junction elements with distributed WERs based on numerical simulations. We simulated Bernoulli trials of writing, assuming that the WER obeys a beta distribution. The results show that for typical writing patterns, WF in a memory cell array obeys a binomial distribution, with the mean of the WER as the probability of success. The statistical properties of WF in a memory cell array are not affected by the variance and skewness of the WER. The results provide a basic understanding of the statistical properties of WF in a memory cell array and will be useful for the development of computing systems that exploit erroneous memories.

Fully micromagnetic analysis of voltage-controlled magnetization switching in magnetic-topological-insulator-based devices

We numerically investigate magnetization switching behavior in voltage-controlled magnetic-topological-insulator-based (VC-MTI) devices by means of the fully micromagnetic simulation. First, the influence of domain in VC-MTI devices was investigated. When the device size is larger than 1 µm, multidomain structure might appear. However, these domains disappear when the gate voltage and source-drain electric field are applied, which is the refresh operation of the actual VC-MTI device. The switching behaviors of a 100-nm-size VC-MTI device in the fully micromagnetic simulation are in agreement with those of the macrospin model although the gate pulse width is slightly different from that of the macrospin model. When the device is less than 1 µm, the macrospin model is adequate for the investigation of switching behavior in VC-MTI devices and the magnetization switching occurs in rotation mode. Therefore, for the VC-MTI device with less-than-100 nm size, the macrospin model is a good approach for the analysis of device operation and write-error rate.

Demonstration of a manufacturable SOT-MRAM multiplexer array towards industrial applications

We have successfully demonstrated a 1 Kb spin-orbit torque (SOT) magnetic random-access memory (MRAM) multiplexer (MUX) array with remarkable performance. The 1 Kb MUX array exhibits an in-die function yield of over 99.6%. Additionally, it provides a sufficient readout window, with a TMR/R P_sigma% value of 21.4. Moreover, the SOT magnetic tunnel junctions (MTJs) in the array show write error rates as low as 10−6 without any ballooning effects or back-hopping behaviors, ensuring the write stability and reliability. This array achieves write operations in 20 ns and 1.2 V for an industrial-level temperature range from −40 to 125 °C. Overall, the demonstrated array shows competitive specifications compared to the state-of-the-art works. Our work paves the way for the industrial-scale production of SOT-MRAM, moving this technology beyond R&D and towards widespread adoption.

Strain-mediated voltage controlled magnetic anisotropy based switching for magnetic memory applications

Reliability and packing density concerns are the two major shortcomings of spin transfer torque and spin orbit torque based magnetic memory, respectively. Voltage controlled magnetic anisotropy (VCMA) becomes energy efficient and fast, showing transcendence for the writing mechanism in the magnetic tunnel junction. Deterministic switching cannot be achieved by VCMA alone in the out of plane nanomagnet. It requires an external in-plane magnetic field, but the use of an external field is inconvenient for on-chip applications. We exploit stress and exchange bias provided by an antiferromagnetic material to mitigate the external magnetic field requisite. We perform macro-spin simulations using the Landau–Lifshitz–Gilbert equation at room temperature. We use the VCMA effect cum stress effect to investigate field free switching performance, and this improves the write error rate (WER) to 5×10−5 against WER of 0.1 with the VCMA effect alone. We studied the effects of applied voltage (amplitude and pulse width), exchange bias field, and VCMA coefficient on the switching performance in detail. This proposed two-terminal device can be helpful in achieving high cell density to implement nonvolatile magnetic memory.

Numerical analysis of voltage-controlled magnetization switching operation in magnetic-topological-insulator-based devices

We theoretically investigate influences of electronic circuit delay, noise, and temperature on write-error-rate (WER) in voltage-controlled magnetization switching operation of a magnetic-topological-insulator-based device by means of the micromagnetic simulation. This device realizes magnetization switching via spin–orbit torque (SOT) and voltage-controlled magnetic anisotropy (VCMA), which originate from the 2D-Dirac electronic structure. We reveal that the device operation is extremely robust against circuit delay and signal-to-noise ratio. We demonstrate that the WER on the order of ∼10−4 or below is achieved around room temperature due to steep change in VCMA. Also, we show that the larger SOT improves thermal stability factor. This study provides a next perspective for developing voltage-driven spintronic devices with ultra-low power consumption.

Progress and Application Perspectives of Voltage‐Controlled Magnetic Tunnel Junctions

AbstractThis article discusses the current state of development, open research opportunities, and application perspectives of electric‐field‐controlled magnetic tunnel junctions that use the voltage‐controlled magnetic anisotropy effect to control their magnetization. The integration of embedded magnetic random‐access memory (MRAM) into mainstream semiconductor foundry manufacturing opens new possibilities for the development of energy‐efficient, high‐performance, and intelligent computing systems. The current generation of MRAM, which uses the current‐controlled spin‐transfer torque (STT) effect to write information, has gained traction due to its nonvolatile data retention and lower integration cost compared to embedded Flash. However, scaling MRAM to high bit densities will likely require a transition from current‐controlled to voltage‐controlled operation. In this perspective, an overview of voltage‐controlled magnetic anisotropy (VCMA) as a promising beyond‐STT write mechanism for MRAM devices is provided and recent advancements in developing VCMA‐MRAM devices with perpendicular magnetization are highlighted. Starting from the fundamental mechanisms, the key remaining challenges of VCMA‐MRAM, such as increasing the VCMA coefficient, controlling the write error rate, and achieving field‐free VCMA switching are discussed. Then potential solutions are discussed and open research questions are highlighted. Lastly, prospective applications of voltage‐controlled magnetic tunnel junctions (VC‐MTJs) in security applications, extending beyond their traditional role as memory devices are explored.

Substantial reduction of write-error rate for voltage-controlled magnetoresistive random access memory by in-plane demagnetizing field and voltage-induced negative out-of-plane anisotropy field

Voltage-controlled magnetoresistive random access memory (VC-MRAM) based on voltage-induced dynamic switching in magnetic tunnel junctions (MTJs) is a promising ultimate non-volatile memory with ultralow power consumption. However, the dynamic switching in a conventional MTJ is accompanied by a relatively high write error rate (WER), hindering the reliable operation of VC-MRAM. Here, we propose a reliable writing scheme using the in-plane demagnetizing field (IDF) and voltage-induced negative out-of-plane anisotropy field (NOAF). Numerical simulations based on macrospin model demonstrate that the voltage induced NOAF modifies the switching dynamics and increases the torque due to the IDF, thereby reducing the switching time. The IDF and voltage-induced NOAF also reduce the mean energy difference between the magnetization direction at the end of the pulse and the equilibrium direction. As a result, an appropriate combination of the IDF and voltage-induced NOAF reduces the WER by one order of magnitude compared with that of the dynamic switching in a conventional MTJ.

Quantifying External Magnetic Field Immunity of the Write Process in Perpendicular Spin-Transfer-Torque Random Access Memory

The resilience of write operation in spin-transfer-torque random access memory (STT-RAM) under external magnetic field disturbances is often overlooked. In this work, write error rates (WER) of STT-RAM are calculated, including the effects of magnetic field perturbation of varying magnitude and direction. WER is calculated directly from the numerical solution of the two-dimensional Fokker-Planck equation that enables the estimation of ultra-low probability tails of WER. The results show orders of magnitude increase in WER when an external magnetic field is applied along a direction non-collinear with the easy axis of the magnet. Numerical results are explained quantitatively from an analytical theory that confirms the appearance of additional zero-torque “stagnation points” on the unit sphere’s surface, representing the magnetization vector of constant magnitude. Simulated bit error rates are calculated under varying applied current and write pulse duration. Implications on the active write mode magnetic immunity are discussed. The results present critical insights into the switching process of perpendicular STT-RAM memory cells exposed to external magnetic field perturbation and call for a thorough characterization of such failure modes for quantifying external magnetic field tolerance.

Characteristic time of transition from write error to retention error in voltage-controlled magnetoresistive random-access memory

Voltage controlled magnetoresistive random access memory (VC MRAM) is a promising candidate for a future low-power high-density memory. The main causes of bit errors in VC MRAM are write error and retention error. As the size of the memory cell decreases, the data retention time decreases, which causes a transition from the write-error-dominant region to the retention-error-dominant region at a certain operating time. Here we introduce the characteristic time of the transition from the write-error-dominant region to the retention-error-dominant region and analyze how the characteristic time depends on the effective anisotropy constant, K0. The characteristic time is approximately expressed as tc=2wτ, where w is the write error rate, and τ is the relaxation time derived by Kalmkov (2004). We show that for large K0, tc increases with increase of K0 similar to τ. The characteristic time is a key parameter for designing the VC MRAM for the variety of applications such as machine learning and artificial intelligence.

Impact of Reference-Layer Stray Field on the Write-Error Rate of Perpendicular Spin-Transfer-Torque Random-Access Memory

A finite-temperature micromagnetic study of magnetization switching and write-error rates in a perpendicular magnetic tunnel junction with and without synthetic antiferromagnetic layer (SAF) is presented. In the absence of SAF, magnetization switching is induced by domain-wall nucleation and propagation. Although the various modes of domain-wall propagation are observed to delay switching, it does not show an appreciable impact on the overall write-error-rate slopes. In the presence of the nonuniform stray field from the SAF assembly, the domain-wall-based switching modes turn on more complex magnetization dynamics that impedes the switching process. In cases where the SAF layers fail to balance each other contributing to a stronger stray field, incoherent switching modes give rise to metastable states with significantly longer lifetimes, and a dramatic change in the write-error slopes is observed. Simulation results are compared to recent experimental findings from time-domain measurements of spin-transfer-torque switching and measurements of anomalous write-error rates. These results directly prove the long-predicted relation of the SAF stray field to write-error anomaly in perpendicular spin-transfer-torque magnetic random-access memory and could be useful to solve the anomalous write-error problems.

Low-Energy Shared-Current Write Schemes for Voltage-Controlled Spin-Orbit-Torque Memory

Voltage-controlled (VC) spin-orbit-torque (SOT) magnetic random access memory (MRAM) is being considered as the next-generation magnetic memory with potential to achieve superior speed, power, and write error rates over existing MRAM technologies. By placing multiple VC devices on a single SOT bus, VC-SOT MRAM can also enable compact structures, in which multiple devices can be addressed individually yet programmed via a shared current. In this work, we propose two implementations of shared-current write: the horizontal shared current write (HSCW), which reduces the average SOT current per bit by the number of bits on the SOT bus, and the vertical shared current write (VSCW), which can further leverage data dependency for increased performance. We simulate the efficiency of the HSCW and VSCW using a Landau–Lifshitz–Gilbert (LLG)-based VC-SOT model and a 28-nm CMOS technology and show that HSCW and VSCW can achieve an energy saving of 74% and 40%–87%, respectively, in a 32-bit setting. Analysis of data patterns in common workloads finds that 40% of data share more than 85% common bits, for which VSCW can leverage for further improved performance.

Comparative Study of Temperature Impact in Spin-Torque Switched Perpendicular and Easy-Cone MTJs

The writing performance of the easy-cone magnetic tunnel junction (MTJ) and perpendicularly magnetized MTJ (pMTJ) under various temperatures was investigated based on the macrospin model. When the temperature is changed from 273 K to 373 K, the switching current density of the pMTJ changes by 56%, whereas this value is only 8% in the easy-cone MTJ. Similarly, the temperature-induced variation of the switching delay is more significant in the pMTJ. This indicates that the easy-cone MTJ has a more stable writing performance under temperature variations, resulting in a wider operating temperature range. In addition, these two types of MTJs exhibit opposite temperature dependence in the current overdrive and write error rate. In the easy cone MTJ, these two performance metrics will reduce as temperature is increased. The results shown in this work demonstrate that the easy-cone MTJ is more suitable to work at high temperatures compared with the pMTJ. Our work provides a guidance for the design of STT-MRAM that is required to operate at high temperatures.

Stochastic Switching in a Magnetic-Tunnel-Junction Neuron and a Bias-Dependent Néel-Arrhenius Model

Back hopping or telegraphic switching describes stochastic bistate oscillation in magnetic tunnel junctions (MTJ) at high bias, which significantly increases the write error rate of memory storage. Nevertheless, this unfavorable stochastic switching could be utilized to construct extremely compact spiking neuron circuits, where both the spike frequency and duty cycle are proportional to the applied bias voltage. This MTJ neuron is the fundamental building block of future all-spin neural networks. This paper analyzes the mechanism of stochastic switching in the MTJ neuron in detail. The self-heating effect at high bias is identified to induce thermal perturbation through a reduced energy barrier of a weakened perpendicular magnetic anisotropy. The high spike frequency is measured up to 10 MHz, which is mainly limited by the transition time between states and the multistate switching when approaching the Curie temperature of the ferromagnetic phase. Finally, to quantitatively describe the stochastic switching phenomenon, we establish a bias-dependent N\'eel-Arrhenius compact model, which calibrates well with experimental data. Based on this model, the potential and design guideline for realizing MTJ neurons with a spike frequency toward the gigahertz range are also discussed.

High-Density Spin–Orbit Torque Magnetic Random Access Memory With Voltage-Controlled Magnetic Anisotropy/Spin-Transfer Torque Assist

This article explores an area saving scheme for spin–orbit torque (SOT) magnetic random access memory (MRAM) by sharing the SOT channel and write transistor among multiple magnetic tunnel junctions (MTJs). We use two write mechanisms to selectively write the MTJs, i.e., voltage-controlled magnetic anisotropy (VCMA)-assisted write in the presence of an external magnetic field and field-free spin-transfer torque (STT)-assisted write. Using micromagnetic simulations that are augmented by the rare-event enhancement, we study various trade-offs among write current, time, and energy, write error rate (WER), and the number of MTJs on an SOT channel. We quantify the issue of IR drop on the SOT channel as a function of the SOT layer thickness and number of MTJs. Our results show having more than four MTJs on an SOT channel poses major challenges in terms of IR drop and WER. In addition, we evaluate the impact of the proposed scheme on read performance.

Heavily Damped Precessional Switching with Very Low Write-Error Rate in Elliptical-Cylinder Magnetic Tunnel Junctions

Voltage-induced dynamic switching in magnetic tunnel junctions (MTJs) is a writing technique for voltage-controlled magnetoresistive random access memory (VCMRAM), which is expected to be an ultimate nonvolatile memory with ultralow power consumption. In conventional dynamic switching, the width of subnanosecond write voltage pulses must be precisely controlled to achieve a sufficiently low write-error rate (WER). This very narrow tolerance of pulse width is the biggest technical difficulty in developing VCMRAM. Heavily damped precessional switching is a writing scheme for VCMRAM with a substantially high tolerance of pulse width, although the minimum WER has been much higher than that of conventional dynamic switching with an optimum pulse width. In this study, we theoretically investigate the effect of MTJ shape and the direction of the applied magnetic field on the WER of heavily damped precessional switching. The results show that the WER in elliptical-cylinder MTJs can be several orders of magnitude smaller than that in usual circular-cylinder MTJs when the external magnetic field is applied parallel to the minor axis of the ellipse. The reduction in the WER is due to the fact that the demagnetization field narrows the component of the magnetization distribution perpendicular to the plane direction immediately before the voltage is applied.

Distribution of write error rate of spin-transfer-torque magnetoresistive random access memory caused by a distribution of junction parameters

Distribution of write error rate (WER) of spin-transfer-torque magnetoresistive random access memory (STT MRAM) caused by a distribution of resistance area product and anisotropy constant is theoretically studied. Assuming that WER is much smaller than unity, and junction parameters obey a normal distribution, we show that the WER obeys a logarithmic normal distribution. We derive analytical expressions for the probability density function and statistical measures. We find that the coefficient of variation of WER can be reduced by decreasing the pulse width. We also perform numerical simulations based on the Fokker–Planck equation and confirm the validity of the analytical expressions. The results are useful for designing reliable STT MRAMs.

Benchmarking of spin–orbit torque vs spin-transfer torque devices

We present a comprehensive benchmarking for spin-transfer torque (STT) and spin–orbit torque (SOT) based random-access memories. Based on experimentally validated micromagnetic simulations along with the use of rare event enhancement techniques, we show various tradeoffs among the write error rate, write time, and write current. We consider both in-plane and perpendicular devices. For SOT driven perpendicular devices, we include various write mechanisms, such as field-assisted, STT-assisted, and switching due to out-of-plane spin torque, usually present in low symmetry materials.

Write Error Rate in Bias-Magnetic-Field-Free Voltage-Induced Switching in a Conically Magnetized Free Layer

Write error rate (WER) in voltage-induced magnetization switching of a conically magnetized free layer with an elliptic cylinder shape is numerically calculated on the basis of the macrospin model. Simulations using the Langevin equation show that a WER lower than the order of ${10}^{\ensuremath{-}5}$, which enables practical WER with a single error-correction process, is theoretically feasible at zero-bias magnetic field and room temperature. We also show that WER at a given thermal stability factor and the volume of the free layer can be reduced by adopting the free layer with the larger in-plane shape anisotropy field and a moderate cone angle at zero-bias voltage.

Nanometer-thin L1-MnAl film with B2-CoAl underlayer for high-speed and high-density STT-MRAM: Structure and magnetic properties

The material development of magnetic tunnel junction with a perpendicular easy axis is in great demand to advance spin-transfer torque magnetoresistive random access memory (STT-MRAM) technologies. To realize high-speed and high-density STT-MRAM, a thin-film magnetic material with large perpendicular anisotropy and small spontaneous magnetization has great potential. Here, we develop a thin-film deposition technique for a-few-nanometer-thin L10-MnAl by sputtering and investigate its structure and magnetic properties. Utilization of the B2-CoAl buffer layer allows us to grow L10-MnAl with a large crystalline anisotropy of 8.5 × 105 J/m3, the small spontaneous magnetization of 0.62 T, and the tolerance for 400 °C annealing even at the MnAl thickness of 2 nm. We calculate the device properties based on the obtained material parameters and find that high retention properties, high-speed switching, and low write-error rate can be obtained at the single-digit-nm region, which are not readily achieved by conventional material systems. The results show the potential of L10-MnAl for high-density and high-speed STT-MRAM.