Write Error Rate Research Articles

Analysis and Compact Modeling of Magnetic Tunnel Junctions Utilizing Voltage-Controlled Magnetic Anisotropy

A macrospin compact model of a perpendicularly magnetized voltage-controlled magnetic tunnel junction (MTJ) is introduced, for the evaluation of electronic and magnetic characteristics associated with its switching behavior. The voltage-driven precessional switching has been shown to outperform current-driven switching in terms of energy, speed, and bit density. However, to realize the device in embedded system memory applications, developing a compact model for simulating hybrid MTJ/CMOS circuits is necessary. This framework also needs to be compatible with conventional computer-aided circuit design tools and flows. In this paper, the voltage-controlled magnetic anisotropy effect is included as a component of the effective magnetic field in a Landau–Lifshitz–Gilbert (LLG) equation-based model. The compact model is described by Verilog-A, providing a numerical solution for a 3-D magnetization trajectory and the corresponding conductance change of the MTJ. We also include the thermal noise effect in the LLG equation to allow the evaluation of stochastic switching behavior under a wide variety of bias conditions, which can be quantified in terms of write error rate (WER). It is shown that the model allows for optimization of write pulse shape and design considerations to achieve the lowest WER for given MTJ parameters.

Reduction in the write error rate of voltage-induced dynamic magnetization switching using the reverse bias method

Using macro-spin modeling, we studied the reduction in the write error rate (WER) of voltage-induced dynamic magnetization switching by enhancing the effective thermal stability of the free layer using a voltage-controlled magnetic anisotropy change. Marked reductions in WER can be achieved by introducing reverse bias voltage pulses both before and after the write pulse. This procedure suppresses the thermal fluctuations of magnetization in the initial and final states. The proposed reverse bias method can offer a new way of improving the writing stability of voltage-driven spintronic devices.

A Variation-Aware Timing Modeling Approach for Write Operation in Hybrid CMOS/STT-MTJ Circuits

In this paper, a variation-aware simulation framework for hybrid circuits comprising MOS transistors and magnetic tunnel junction (MTJ) devices is presented. The framework is based on one-time characterization via micromagnetic multi-domain simulations, overcoming the inaccuracies introduced by single-domain analysis, which most of the existing frameworks are based on. As further distinctive capability, non-Gaussian stochastic variations of the MTJ write switching time are explicitly modeled through a Skew Normal distribution, making the model suitable for low-power and low-voltage designs. The framework involves the use of a Verilog-A look-up table-based model, which assures easy integration with commercial design tools. Our strategy is evaluated on a spin-transfer torque-magnetoresistive random access memory (MRAM) working in RAM and true random number generator (TRNG) modes. In RAM mode, while the commonly-used approach based on Gaussian-distributed switching statistics tends to underestimate the pulse width required for a write error rate of $10^{-6}$ by about 20%, our Skew Normal-based strategy allows tracking reference micromagnetic results with an average error less than 4%. In TRNG mode, our approach also allows a better tracking of the reference 50%-switching probability contour with an error less than 1%abs. However, the incorporation of the Skew Normal distribution in our Verilog-A model results in an increase of the CPU time by 50% on average as compared with the use of the built-in statistical functions.

Write Modeling and Read Signal Processing for Heat-Assisted Bit-Patterned Media Recording

Heat-assisted bit-patterned media recording (HABPMR) can significantly improve channel areal density due to the increased effective write field gradient provided by heat assistance and decreased media jitter offered by bit-patterned media. In this paper, an analytical write channel model, which can accurately capture the effects of Curie temperature, magnetic island position and size, anisotropy field, and write clock frequency fluctuations, is introduced and investigated for HABPMR. For read signal processing study, a read channel characterizing the media noise and reader geometry is combined with a data-dependent write channel to obtain the readback signal. In addition, the allowable write window offsets, write error rate during the write process and the bit error rate after readback as function of various noise sources are studied. Furthermore, 2-D equalization followed by the Bahl-Cocke-Jelenik-Raviv detector combined with picket-shift code is used to mitigate the 2-D interference and correct the burst errors caused by the write clock mis-synchronization. It is shown, via numerical experiments, that the proposed approach can provide significant symbol error rate performance improvement compared to a channel with conventional Reed Solomon code.

Fast Low-Current Spin-Orbit-Torque Switching of Magnetic Tunnel Junctions through Atomic Modifications of the Free-Layer Interfaces

Future applications of spin-orbit torque will require new mechanisms to improve the efficiency for switching nanoscale magnetic tunnel junctions (MTJs), while also controlling the magnetic dynamics to achieve fast, nanosecond scale performance with low write error rates. Here we demonstrate a strategy to simultaneously enhance the interfacial magnetic anisotropy energy and suppress interfacial spin memory loss by introducing sub-atomic and monatomic layers of Hf at the top and bottom interfaces of the ferromagnetic free layer of an in-plane magnetized three-terminal MTJ device. When combined with a beta-W spin Hall channel that generates spin-orbit torque, the cumulative effect is a switching current density of 5.4 x 106 A/cm2, more than a factor of 3 lower than demonstrated in any other spin-orbit-torque magnetic memory device at room temperature, and highly reliable switching with current pulses only 2 ns long.

Efficient cache replacement policy for minimising error rate in L2-STT-MRAM caches

The current research statistics for cache designing reveals that Spin Torque Transfer Magnetic RAMs (STT-MRAMs) have become one of the most promising technologies in the field of memory chip design, gaining a lot of attention from researchers due to its dynamic direct map and data access policies for reducing the average cost i.e. both time and energy optimisation. In this paper, the vulnerability of STT-MRAM caches has been investigated to examine the effect of workloads as well as process variations for characterising the reliability of STT-MRAM cache. The current study is intended to analyse and evaluate an existing efficient cache replacement policy namely Least Error Rate (LER) which utilises Hamming Distance (HD) computations to reduce the Write Error Rate (WER) of L2-STT-MRAM caches with acceptable overheads. The performance analysis of the algorithm ensures its effectiveness in reducing the WER and cost overheads as compared to the conventional LRU techniques.

Efficient cache replacement policy for minimising error rate in L2-STT-MRAM caches

The current research statistics for cache designing reveals that Spin Torque Transfer Magnetic RAMs (STT-MRAMs) have become one of the most promising technologies in the field of memory chip design, gaining a lot of attention from researchers due to its dynamic direct map and data access policies for reducing the average cost i.e. both time and energy optimisation. In this paper, the vulnerability of STT-MRAM caches has been investigated to examine the effect of workloads as well as process variations for characterising the reliability of STT-MRAM cache. The current study is intended to analyse and evaluate an existing efficient cache replacement policy namely Least Error Rate (LER) which utilises Hamming Distance (HD) computations to reduce the Write Error Rate (WER) of L2-STT-MRAM caches with acceptable overheads. The performance analysis of the algorithm ensures its effectiveness in reducing the WER and cost overheads as compared to the conventional LRU techniques.

Etching Methods for STT-MRAM

Spin-transfer torque [1] MRAM (STT-MRAM) continues to be the subject of intense investigation due to its scalability and excellent endurance. Initially explored mainly as a DRAM replacement, STT-MRAM with perpendicularly magnetized materials is now targeted as a nonvolatile memory, medium-performance replacement for mobile applications, and more long term as a fast, dense, cache memory. This talk will review MRAM magnetic stack etching methods and related aspects of integration, with particular reference to STT-MRAM. An STT-MRAM memory cell, which consists of a magnetic tunnel junction (MTJ) and a transistor, has the attractive property that if the critical current density for spin-torque switching (Jc) remains constant, then the critical current for MTJ switching (Ic) will scale as λ2, where λ is MTJ diameter . Thus, scaling is highly desirable for STT-MRAM. A significant research effort is also being devoted to developing MTJs with perpendicular magnetic anisotropy (PMA) materials [2] to achieve acceptably low switching currents, e.g., < 25 uA. Scaling is not without challenges, however, and the STT-MTJ arrays must, e.g., exhibit sufficient statistical margins between reading and writing operations, and must satisfy other key design properties including, a) sufficient TMR for the read signal, and b) a high enough energy barrier for up to 10 years of data retention. It has been found that fabrication processes like MTJ etching play key roles in MTJ performance to realize the full potential of newly-developed PMA materials, e.g., the ability to approach the resistance-area product RA measured by current-in-plane tunneling (CIPT) [3] on unprocessed MRAM stacks. The semiconductor industry seems to be preparing for large-scale manufacturing of STT-MRAM, by converging on an IBE-centered etching approach, followed by in situencapsulation. Minimizing metallic redeposition on the edge of the tunnel barrier during etching, and of edge-related magnetic damage, are key challenges in STTM patterning using IBE. Ohsawa et al. [4] showed that a typical MRAM IBE etching energy, e.g., 200 eV, causes a damage layer several monolayers thick at the patterned surface, suggesting that lower beam energies would be necessary during etching, or at least in the final damage-removal step. Confirming the promise of IBE, Samsung researchers Song et al. [5] recently reported high yields for an embedded STT-MRAM, patterned using IBE, with 8-Mbit density and a cell size of 0.0364 sq. micron. At IBM, following conventional 193 nm lithography, we have typically employed a RIE etch to pattern a Ta-based MTJ hardmask, stopping on a protective cap layer, which is then followed by MRAM stack etching using a combination of a MeOH-based RIE and IBE. Using arrays of different lithographically-printed MTJ mask diameters, final etched device sizes ranging from a high of about 100 nm down to 10 nm or less are typically obtained, as confirmed by TEM [6, 7]. Using this patterning approach, we demonstrated good STT performance down to 10-6 write-error-rate (WER) in a wide range of device sizes from 50 nm to 11 nm for a specific PMA STT-MRAM stack, for a statistically relevant sample of more than 650 devices [7]. We further demonstrated an individual 11 nm device switching down to WER = 7*10-10at 10 ns using only 7.5 uA current. [1] J. C. Slonczewski, J. Magn. Magn. Mater.,159, L1 (1996). [2] For ex., D. C. Worledge et al., IEDM Tech. Dig., 296 (2010); S. Ikeda et al., Nature Mater., 9, 721 (2010). [3] D. C. Worledge and P. L. Trouilloud, Appl. Phys. Lett., 83, 84 (2003). [4] Y. Ohsawa et al., IEEE Trans. Magn., 52, 1 (2016). [5] Y.J. Song et al., IEDM, paper 27.2, (2016). [6] M. Gajek et al., Appl. Phys. Lett., 100, 132408 (2012). [7] J. J. Nowak et al., IEEE Magn. Lett., 7, 1 (2016). Acknowledgements We wish to thank E. Galligan, for technical support. The authors gratefully acknowledge the efforts of the staff of the Microelectronics Research Laboratory (MRL) at the IBM T. J. Watson Research Center, where the magnetic device layers were fabricated.

Reduction in write error rate of voltage-driven dynamic magnetization switching by improving thermal stability factor

In this study, we demonstrate voltage-driven dynamic magnetization switching for the write error rate (WER) of the order of 10−5. The largest voltage effect on the perpendicular magnetic anisotropy in Ta/(CoxFe100–x)80B20/MgO structure (x = 0, 10, 31, 51) is obtained for x = 31 after annealing at 250 °C. Based on investigations using perpendicularly magnetized magnetic tunnel junctions that have different (Co31Fe69)80B20 free layer thicknesses, we demonstrate that the improvement in the thermal stability factor is important to reduce the WER. Our results will facilitate the design of highly reliable, voltage–torque, magnetoresistive random access memory.

A Word Line Pulse Circuit Technique for Reliable Magnetoelectric Random Access Memory

A word line pulse (WLP) circuit scheme is proposed toward the implementation of magnetoelectric random access memory (MeRAM). The circuit improves the write error rate (WER) and cell area efficiency by generating a better write pulse compared to conventional bitline pulse (BLP) techniques in terms of the pulse slew rate and amplitude. For the voltage-controlled magnetic anisotropy-induced precessional switching of the magnetic tunnel junction (MTJ), the write pulse shape has a large impact on the switching probability. Typically, a square shape pulse results in higher switching probability compared to that of a triangular shape pulse with long rise and falling edges, since the square shape pulse causes a more stable precessional trajectory of the free layer magnetization by providing a relatively constant in-plane-dominant effective field. Compared to the BLP scheme, the WLP can generate a better square shape pulse by eliminating discharge paths under the pulse condition, using the gain of the access transistor, and effectively diminishing the capacitive loading which needs to be driven. A macrospin compact model of voltage-controlled MTJ shows that the WLP can improve WER by ${10}^{7}$ times and allow MeRAM to have four-time improvement in area efficiency of driver circuits compared to the BLP.

Improved read disturb and write error rates in voltage-control spintronics memory (VoCSM) by controlling energy barrier height

A hybrid writing scheme that combines the spin Hall effect and voltage-controlled magnetic-anisotropy effect is investigated in Ta/CoFeB/MgO/CoFeB/Ru/CoFe/IrMn junctions. The write current and control voltage are applied to Ta and CoFeB/MgO/CoFeB junctions, respectively. The critical current density required for switching the magnetization in CoFeB was modulated 3.6-fold by changing the control voltage from −1.0 V to +1.0 V. This modulation of the write current density is explained by the change in the surface anisotropy of the free layer from 1.7 mJ/m2 to 1.6 mJ/m2, which is caused by the electric field applied to the junction. The read disturb rate and write error rate, which are important performance parameters for memory applications, are drastically improved, and no error was detected in 5 × 108 cycles by controlling read and write sequences.

Fabrication of a magnetic-tunnel-junction-based nonvolatile logic-in-memory LSI with content-aware write error masking scheme achieving 92% storage capacity and 79% power reduction

A magnetic-tunnel-junction (MTJ)-based video coding hardware with an MTJ-write-error-rate relaxation scheme as well as a nonvolatile storage capacity reduction technique is designed and fabricated in a 90 nm MOS and 75 nm perpendicular MTJ process. The proposed MTJ-oriented dynamic error masking scheme suppresses the effect of write operation errors on the operation result of LSI, which results in the increase in an acceptable MTJ write error rate up to 7.8 times with less than 6% area overhead, while achieving 79% power reduction compared with that of the static-random-access-memory-based one.

$1\times$ - to $2\times$ -nm perpendicular MTJ Switching at Sub-3-ns Pulses Below $100~\mu$ A for High-Performance Embedded STT-MRAM for Sub-20-nm CMOS

Magnetization switching is confirmed for sub-3-ns pulses below $100~\mu \text{A}$ in perpendicular magnetic tunnel junctions (MTJs) down to 16 nm in diameter. The magnetoresistance ratio exceeded 150%, satisfying requirements for fast read conditions. Using sub-30-nm MTJs, write-error rates of up to an order of −6 (10−6) are demonstrated. Read and write current margins, which are important device designs, are sufficiently large to avoid read disturbances. Moreover, $1\times $ -to- $2\times $ -nm MTJs have sufficient data retention for level-2 or level-3 cache requirements. Furthermore, the MTJ resistance remains stable after 1012 write events. To the best of our knowledge, this is the first demonstration of $1\times $ - to $2\times $ -nm MTJs supporting cache memory along with read–write current margins, fast read operations, low power consumption, sufficient retention, and high endurance.

Write Error Rate and Read Disturbance in Electric-Field-Controlled Magnetic Random-Access Memory

We report experimental results on write error rate and read disturbance as a function of read/write pulse width and amplitude in electric-field-controlled magnetic tunnel junctions (MTJs). Results are shown for 50 nm perpendicular MTJs. We also design and simulate the performance of a 256 kilobit (Kbit) magneto-electric random-access memory (MeRAM) macro in a 28 nm complementary metal-oxide semiconductor (CMOS) process, based on the measured MTJ device data. The results show that existing electric-field-controlled MTJs are capable of delivering write error rates below $10^{{-9}}$ for 10 ns total write and verify time and read disturbance below $10^{{-16}}$ for 2 ns read time in a 256 Kbit MeRAM array.

MEMRES: A Fast Memory System Reliability Simulator

With scaling technology, emerging nonvolatile devices, and data-intensive applications, memory faults have become a major reliability concern for computing systems. With various hardware and software approaches proposed to address this issue, a comprehensive evaluation is required to understand the effectiveness of these solutions. Considering the complex nature of various memory faults as well as interactions between various correction mechanisms, we propose MEMRES, a fast main memory system reliability simulator. It enables memory fault simulation with error-correcting code (ECC) algorithms and modern memory reliability management, including memory page retirement, mirroring, scrubbing, and hardware sparing. MEMRES is computationally efficient in obtaining memory failure probabilities in the presence of multiple failure mechanisms and complex correction scheme, allowing the optimization of memory system reliability, the prediction of emerging memory reliability, and designing a reliability enhancement technique. The accuracy of MEMRES is verified by an existing analytical model and an existing memory fault simulator. We performed a case study on spin-transfer torque random access memory (STT-RAM)-based main memory, and the results indicate that in-memory ECC can significantly mitigate the write error rate of STT-RAM, demonstrating the capability of handling emerging memory system.

Voltage-controlled magnetization switching in MRAMs in conjunction with spin-transfer torque and applied magnetic field

Voltage-controlled magnetic anisotropy (VCMA) effect has attracted a significant amount of attention in recent years because of its low cell power consumption during the anisotropy modulation of a thin ferromagnetic film. However, the applied voltage or electric field alone is not enough to completely and reliably reverse the magnetization of the free layer of a magnetic random access memory (MRAM) cell from anti-parallel to parallel configuration or vice versa. An additional symmetry-breaking mechanism needs to be employed to ensure the deterministic writing process. Combinations of voltage-controlled magnetic anisotropy together with spin-transfer torque (STT) and with an applied magnetic field (Happ) were evaluated for switching reliability, time taken to switch with low error rate, and energy consumption during the switching process. In order to get a low write error rate in the MRAM cell with VCMA switching mechanism, a spin-transfer torque current or an applied magnetic field comparable to the critical current and field of the free layer is necessary. In the hybrid processes, the VCMA effect lowers the duration during which the higher power hungry secondary mechanism is in place. Therefore, the total energy consumed during the hybrid writing processes, VCMA + STT or VCMA + Happ, is less than the energy consumed during pure spin-transfer torque or applied magnetic field switching.

Improving Write Performance for STT-MRAM

Spin-transfer-torque magnetic random access memory (STT-MRAM) is a promising emerging memory technology because of its various advantageous features such as scalability, non-volatility, density, endurance, and soft-error immunity. However, high write energy and long write latency are the major obstacles for this technology. The long write latency of the STT-MRAM is primarily due to two reasons. First, the bit-cell switching is asymmetric, which means that one write direction is significantly slower than the other. Second, the stochastic switching behavior of the bit-cell mandates a significant margin for a target write error rate (WER). In this paper, we propose static and dynamic circuit-level techniques to reduce the overall write latency. The static technique reduces the impact of write asymmetry by increasing the write current only for the slow writes. The dynamic technique additionally targets the write margin by dynamically increasing the write current in a stepwise manner to mitigate the negative impact of the stochastic switching behavior. Experimental results show that our proposed dynamic method can reduce the overall write latency by 71% while maintaining the same WER. Applying this technique to a 512 kB L2-cache of a microprocessor improves its performance by 11% and saves energy by 10% on average.

High-Speed, Low-Power, and Error-Free Asynchronous Write Circuit for STT-MRAM and Logic

Benefiting from its simple switching scheme (only a bidirectional current source), high-speed and low-power spin-transfer torque (STT) has been regarded as one of the most promising switching mechanisms for a magnetic tunnel junction (MTJ)-based non-volatile memory and logic circuits. However, it suffers from a number of reliability issues like write error induced by its intrinsic stochasticity, process variation, and so on. In order to reduce the write error rate, the mainstream solution is to enlarge the write pulse duration at the expense of write energy dissipation. Some self-terminated write circuits have been proposed to avoid the wasted write energy. But the hardware cost of these write circuits is especially large. In this paper, a novel cost-efficient self-terminated write circuit is proposed using two simple built-in sensing circuits. The proposed write circuit is simulated with a physics-based STT-MTJ compact model and a commercial CMOS 40 nm design kit. The simulation result shows about 35% reduction of circuit area and 10% lower energy consumption in comparison with that in prior work. In addition, the Error-Free write operation under process variation of both the CMOS transistor and the STT-MTJ is achieved due to its large sense margin ( $\sim 320$ mV).

Experimental Observation of Back-Hopping With Reference Layer Flipping by High-Voltage Pulse in Perpendicular Magnetic Tunnel Junctions

Low write error rate (WER) is an important requirement for spin-transfer torque magnetic random access memory to be developed as a product. However, there have been reports about back-hopping phenomena that disturb achieving low WER. We demonstrate the experimental observation of back-hopping from the behavior of the WER in perpendicular magnetic tunnel junctions. WER decreases as pulse voltage (Vp) increases, but increases back as Vp increases further. It is attributed to the back-hopping, which originates from flipping of the reference layer (RL) and consequent alternating reversal of RL and free layer. Thus, it is necessary for the RL to be more stable and robust to avoid the back-hopping and to achieve low WER. We performed switching experiments on the devices of different stacks, which reveal back-hopping was the most severe in a magnetic tunnel junction device with the weakest coupling strength of the RL, and was significantly suppressed with a strongly coupled RL.

Nanosecond-Timescale Low Energy Switching of In-Plane Magnetic Tunnel Junctions through Dynamic Oersted-Field-Assisted Spin Hall Effect.

We investigate fast-pulse switching of in-plane-magnetized magnetic tunnel junctions (MTJs) within 3-terminal devices in which spin-transfer torque is applied to the MTJ by the giant spin Hall effect. We measure reliable switching, with write error rates down to 10-5, using current pulses as short as just 2 ns in duration. This represents the fastest reliable switching reported to date for any spin-torque-driven magnetic memory geometry and corresponds to a characteristic time scale that is significantly shorter than predicted possible within a macrospin model for in-plane MTJs subject to thermal fluctuations at room temperature. Using micromagnetic simulations, we show that in the three-terminal spin-Hall devices the Oersted magnetic field generated by the pulse current strongly modifies the magnetic dynamics excited by the spin-Hall torque, enabling this unanticipated performance improvement. Our results suggest that in-plane MTJs controlled by Oersted-field-assisted spin-Hall torque are a promising candidate for both cache memory applications requiring high speed and for cryogenic memories requiring low write energies.