High-Speed, Low-Power, and Error-Free Asynchronous Write Circuit for STT-MRAM and Logic

Abstract

Benefiting from its simple switching scheme (only a bidirectional current source), high-speed and low-power spin-transfer torque (STT) has been regarded as one of the most promising switching mechanisms for a magnetic tunnel junction (MTJ)-based non-volatile memory and logic circuits. However, it suffers from a number of reliability issues like write error induced by its intrinsic stochasticity, process variation, and so on. In order to reduce the write error rate, the mainstream solution is to enlarge the write pulse duration at the expense of write energy dissipation. Some self-terminated write circuits have been proposed to avoid the wasted write energy. But the hardware cost of these write circuits is especially large. In this paper, a novel cost-efficient self-terminated write circuit is proposed using two simple built-in sensing circuits. The proposed write circuit is simulated with a physics-based STT-MTJ compact model and a commercial CMOS 40 nm design kit. The simulation result shows about 35% reduction of circuit area and 10% lower energy consumption in comparison with that in prior work. In addition, the Error-Free write operation under process variation of both the CMOS transistor and the STT-MTJ is achieved due to its large sense margin ( $\sim 320$ mV).