Worst-case Corner Research Articles

Design of low power and low phase noise LC-VCO for Bluetooth/WLAN applications

The proposed Inductor-Capacitor Voltage-Controlled Oscillator (LC-VCO) prototype design generates 2.45 GHz to 4.58 GHz of frequency using the Cadence UMC 180 nm process with a 1.8V supply. This architecture carried a new viewpoint on tank design put forth by enhancing the varactor tuning. Here, the circuit employs a CMOS differential cross-coupled pair, and rail-to-rail DC biasing achieves a higher voltage swing. Simulation analysis parameters are measured at 2.45 GHz frequency, phase noise is −123.5 dBc/1 MHz offset, power is 3.5 mW, jitter is 0.232 fsec, and it occupies 0.118 μm2 layout area. Additionally, the simulations have been extended for analysis under Process Voltage and Temperature Corners, Monte-Carlo, and Worst-Case Corners. This study obtained a better FoM of -200.94 dBc/Hz. The simulation results and FoM of the proposed design show a considerably improved than state-of-the-art framework. This LC-VCO circuit study will be suitable for implementing the sub-6 GHz charge pump phase-locked loops (CP-PLLs) system for 5G applications.

In-depth Multi-Objective charge pump design space exploration towards the automatic synthesis of power management units

The inclusion of automation mechanisms in the intricate design of power management units (PMUs) is long pursued in industry. This paper addresses a mixed-signal design flow whose purpose is to automatically produce, from the system-level to the ready-for-tape-out layout, complex PMUs when given a set of specifications. Particularly, in that flow, at the IP level, the proper analysis of the design tradeoffs is tedious and impractical, as a large amount of conflicting performance figures obtained from transient analysis for typical and multiple process/temperature corners, must be considered simultaneously. Therefore, it is common for the design cycle of a single integrated charge pump required in a state-of-the-art PMU to surpass a full month, depending on the intended technology, devices’ types and operation voltages. Additionally, by the end of this process, circuit designers often end up with a limited vision of the attainable performances. However, due to the recent improvements in computational power of modern workstations, optimization-based techniques with expensive evaluation mechanisms are now perceived as a potential solution to pursue optimal sizing and layout. Therefore, an academic electronic design automation tool is adapted and applied to explore the performance boundaries of a charge pump in a 180-nm technology node and determine the optimal tradeoffs between performance and the, severely constrained, layout area. In the last step, a worst-case corner optimization on a 45- and 99- dimensional design and performance spaces, respectively, derived from 9 time-consuming transient analysis of each candidate solution, produced 35 design solutions that provide a thorough analysis between worst-case efficiency, voltage drop, and rise and fall times, impossible to perform in the manual design. The obtained insights on the design space were used to speed-up the process of devising a solution for tape-out.

AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Error-Efficient Computing

As the timing guardband consumes more and more design margin with the technology scaling, better-than-worst-case (BTWC) techniques have gained more attention as a promising solution. BTWC techniques can relax the design margin by transcending the pessimistic static timing constraints and utilizing the dynamic timing information. However, to guarantee the design reliability throughout the lifetime, the conventional dynamic timing analysis (DTA) engines need an extra reliability guardband, which is commonly evaluated under the worst-case corners of aging and variation. This type of guardbanding consumes the precious design margin, thus hindering the efficiency improvement from BTWC techniques. Therefore, in this paper, we propose AVATAR, an aging-and variation-aware dynamic timing analyzer that can perform DTA with the impact of transistor aging and random process variation, including the gate-level aging analysis and random variation model that can accurately calculate cell delay under the impact of transistor aging and random variation, and an event-based DTA algorithm that avoids the pessimistic property of graph-based analysis. We also propose an ML-assisted DTA acceleration flow for the multicycle DTA of homogeneous multicore designs. We present two case studies using AVATAR to show its effectiveness. First, we present an application-based dynamic-voltage-frequency-scaling (DVFS) design methodology based on AVATAR, which can exploit application-level dynamic timing slack (DTS) to improve energy efficiency and performance. The results demonstrate that, compared to the design based on the conventional corner-based DTA, the additional performance improvement of the design based on AVATAR can be up to 14% or the additional power-saving can be up to 20%. Second, we demonstrate using the proposed ML-assisted acceleration flow for reliability-aware deep neural network (DNN) accelerator simulation. We use the proposed flow to estimate the impact of timing errors due to aging and random variation on the inference accuracy of two benchmark DNNs. The results demonstrate that the proposed acceleration flow achieves up to 10W speedup with an average error of less than 2%.

Design of robust analog integrated circuit based on process corner performance variability minimization

A novel technique of performance optimization along with fabrication process variation tolerance of integrated circuits is proposed in this work. It is well-known that the probability of chip being manufactured under normal process environment is higher than the other corner process environments since it follows a Gaussian distribution. In this proposed approach Process Corner Performance Variability Minimization (PCPVM) is carried out simultaneously with performance optimization. In PCPVM the statistical performance deviations of the corner cases from the nominal case is minimized by considering the actual SPICE (Simulation Program with Integrated Circuit Emphasis) parameters of different process corners for performance evaluation. The proposed design is made robust by optimizing the circuit performance in nominal case and, also minimizing the difference between chip performances in nominal and worst case corner environments. This approach is expected to improve the performance of the ICs manufactured even under extreme process corner conditions. The proposed technique is validated in two example cases of current starved voltage controlled oscillator and Operational Transconductance Amplifier.

Analysis of Pre-Driver and Last-Stage Power-Ground-Induced Jitter at Different PVT Corners.

This paper presents the study of power/ground (P/G) supply-induced jitter (PGSIJ) on a cascaded inverter output buffer. The PGSIJ analysis covers the IO buffer transient simulation under P/G supply voltage variation at three process, voltage, and temperature (PVT) corners defined at different working temperatures and distinct DC supply voltages at the pre-driver (i.e., /) and last stage (i.e., ). Firstly, the induced jitter contributions by the pre-driver, as well as the last, stage are compared and studied. Secondly, the shared and decoupled P/G supply topologies are investigated. The outcomes of these simulation analyses with respect to worst case jitter corners are determined, while highlighting the importance of modeling the pre-driver circuit behavior to include the induced jitter in the input–output buffer information specification (IBIS)-like model. Accordingly, the measured PGSIJ depends on the corners to be analyzed and, therefore, the designer needs to explore the worst-case corner for the driver’s technology node and the most supply voltage noise affecting the jitter output for signal and power integrity (SiPI) simulations. Finally, the jitter transfer function sensitivity to the amplitude and frequency/phase variations of the separate and combined impacts of the pre-driver and last stage are explored, while discussing the superposition of the power supply induced jitter (PSIJ) induced by both the driver’s IO stages under small signal and large signal supply voltage variations. The linear superposition of the separate PSIJ effects by the pre-driver and last stage depends on the amplitude of the variation of the supply voltage that can drive the transistor to their nonlinear working regions.

Design of a High Performance 1 Kb SRAM Array Using Proposed Soft Error Hardened 12T SRAM Cell

The shrinking of technology node and supply voltage has a profound effect on various design metrics of the SRAM cell. Available SRAM designs in the literature suffer from half-select issue, increased write delay, leakage power, read power, and lower critical charge. Considering the above concerns, a new P12T SRAM cell was proposed incorporating the cross-point selection to remove half-select issue, adding the inverter between the storage nodes to enhance critical charge, High-[Formula: see text] transistors in read path to reduce the read power and leakage power. The critical charge of P12T SRAM cell is 9.13% and 15.21% higher than the 8T and 10T SRAM cells, respectively, at 0.9[Formula: see text]V [Formula: see text]. P12T SRAM cell has 41.61% and 21.4% decrease in read power than 8T and AS10T SRAM cells, respectively, at SS corner for 0.9[Formula: see text]V [Formula: see text]. In P12T SRAM cell, write 1 PDP at worst case corner SS is [Formula: see text], [Formula: see text], [Formula: see text], [Formula: see text], and [Formula: see text] lower than 8T, AS8T, AS10T, 10T, and 12T SRAM cells, respectively, at 0.9[Formula: see text]V [Formula: see text]. Monte Carlo simulation has been done to study variability and half-select issue. 1[Formula: see text]Kb bit interleaving SRAM array is designed using P12T SRAM cell and 12T SRAM cell. 1[Formula: see text]Kb SRAM array using P12T SRAM cell has superior write PDP than 12T SRAM cell. Postlayout simulation has been carried out on all the SRAM cells to estimate different metrics in 45[Formula: see text]nm technology using the Cadence Virtuoso.

Machine Learning for On-the-Fly Reliability-Aware Cell Library Characterization

Aging-induced degradation imposes a major challenge to the designer when estimating timing guardbands. This problem increases as traditional worst-case corners bring over-pessimism to designers, exacerbating competitive and close-to-the-edge designs. In this work, we present an accurate machine learning approach for aging-aware cell library characterization, enabling the designer to evaluate their circuit under the impact of precisely selected degradation. Unlike state of the art, we bring cell library characterization to the designer, empowering their capability in exploring the impact of aging while protecting confidential information from the foundry at the same time. Furthermore, the fast inference of cell libraries makes it feasible, for the first time, to examine aging-induced variability analysis in a Monte-Carlo fashion. Finally, we show that the designer is able to select a less pessimistic timing guardband by choosing adequate delta threshold voltage ( ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) for their design and their needs. Our machine learning approach reaches an R <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> score of $>99\%$ for almost all data stored in the cell library. Only timing constraints show slightly less accuracy with an R <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> score around 95%. When using ML-characterized libraries in static timing analysis, we achieve errors smaller than ±0.5% and ±0.1% for path delay and dynamic power, respectively. Errors in leakage power are negligible and even smaller by orders of magnitude. Our machine learning implementation for standard cell library characterization is publicly available. Download: https://opensource.mlcad.org

Design of a 4.2-to-5.1 GHz Ultralow-Power Complementary Class-B/C Hybrid-Mode VCO in 65-nm CMOS Fully Supported by EDA Tools

Optimal voltage-controlled oscillator (VCO) design for ultralow-power (ULP) radios has to fulfill simultaneously multiple requirements such as frequency tuning range, phase noise, power consumption, and frequency pushing. The manual design struggles to approach the full potential that a given topology can achieve. In this work, we prove the role of electronic design automation (EDA) tools by fully supporting the complex design of a ULP complementary Class-B/C hybrid-mode VCO. In the 1st step of the EDA-assisted flow, we perform a worst-case corner of worst-case tuning sizing optimization over a 108-dimensional performance space, offering sizing solutions with power consumption down to $145~\mu \text{W}$ at the worst-case. In the 2nd step, we introduce an automatic layout generation tool to offer valuable insights into the post-layout design space and devise a ready-for-tape-out fine optimization strategy. The hybrid-mode VCO prototyped in 65-nm CMOS occupies a die area of 0.165 mm2 and dissipates $297~\mu \text{W}$ from a 0.8 V supply at 5.1 GHz. The phase noise at 1 MHz offset is −110.1 dBc/Hz, resulting in a competitive Figure-of-Merit (FoM) of 189.4 dBc/Hz well-suited for ULP applications.

A Method to Utilize Mismatch Size to Produce an Additional Stable Bit in a Tilting SRAM-Based PUF

A new concept for Physical Unclonable Functions (PUFs), the Mirror PUF, is proposed. The Mirror PUF can be applied to existing preselected PUF circuits by post-processing the preselection test results and has the potential to double the number of effective bits, with no additional area at the bit-cell level. The Mirror PUF utilizes a preselection test, which measures the amount of mismatch within the PUF cell. This data is generally used to determine the mask for a conventional PUF. Here, it is used as an entropy source that is not correlated to the original response of the PUF. Bit-cells with low mismatch are considered as a ‘0’ and cells with high mismatch as a ‘1’. A systematic method is shown for identifying unstable bits in the Mirror PUF response. It classifies the cells to ‘low’, ‘medium’ and ‘high’ mismatch, such that medium mismatch bits are considered as unstable and masked from the response. The concept was applied to a 65nm Si implementation of the Capacitive Tilt PUF (Shifman et al., 2020). All of the unstable cells of the Mirror PUF, except for 0.03%, were identified and masked, with a worst-case corner Bit Error-Rate (BER) of only 2.35E-5 and 0.00026% erroneous responses across all corners. The application of the Mirror PUF to the Capacitive tilt PUF increased the number of stable response bits by 66%. No observable correlation was found between the responses of the original PUF and the Mirror PUF.

Many-Objective Sizing Optimization of a Class-C/D VCO for Ultralow-Power IoT and Ultralow-Phase-Noise Cellular Applications

In this paper, the performance boundaries and corresponding tradeoffs of a complex dual-mode class-C/D voltage-controlled oscillator (VCO) are extended using a framework for the automatic sizing of radio frequency integrated circuit blocks, where an all-inclusive test bench formulation enhanced with an additional measurement processing system enables the optimization of “everything at once” toward its true optimal tradeoffs. VCOs embedded in the state-of-the-art multistandard transceivers must comply with extremely high performance and ultralow power requirements for modern cellular and Internet of Things applications. However, the proper analysis of the design tradeoffs is tedious and impractical, as a large amount of conflicting performance figures obtained from multiple modes, test benches, and/or analysis must be considered simultaneously. Here, the dual-mode design and optimization conducted provided 287 design solutions with figures of merit above 192 dBc/Hz, where the power consumption varies from 0.134 to 1.333 mW, the phase noise at 10 MHz from −133.89 to −142.51 dBc/Hz, and the frequency pushing from 2 to 500 MHz/V, on the worst case of the tuning range. These results pushed this circuit design to its performance limits on a 65-nm CMOS technology, reducing 49% of the power consumption of the original design while also showing its potential for ultralow power with more than 93% reduction. In addition, worst case corner criteria were also performed on the top of the worst case tuning range optimization, taking the problem to a human-untrea table LXVI-D performance space.

A non-Monte-Carlo Methodology for Variability Analysis of Magnetic Tunnel Junction Based Circuits

This paper presents a non-Monte Carlo (MC) methodology for variability analysis of spin transfer torque magnetic tunnel junction (STT-MTJ)-based circuits. The methodology is implemented by using worst case corner models of STT-MTJ and transistor. The MTJ compact model of worst case corners is proposed for the first time. The design specifications are detailed in non-volatile memory cells and arithmetic unit, e.g., one transistor–one MTJ (1T-1M) memory array, pre-charge sense amplifier (PCSA)-based STT-MRAM and magnetic full-adder circuit. The methodology is implemented by using a 28 nm fully depleted silicon on insulator design kit and this compact model of MTJ. Results show that the proposed methodology is much more efficient than conventional MC method while keeping the same target of performance evaluation. The simulation speed has been improved up to $226\times $ for an effective evaluation of circuit performance (compared with 1000 times MC simulation). MTJ-based circuit designers can assess the impact of process variation on circuit performance without time consuming MC simulations by using this method.

SafeRazor: Metastability-Robust Adaptive Clocking in Resilient Circuits

Razor-based circuits can run faster or at a lower voltage than those designed to work at the worst case corner. However, all known implementations are prone to failures due to the non-deterministic timing behavior introduced by metastability, even in the case where sufficient time is left for resolution. This paper analyzes the causes why Razor-based circuits fail and proposes a new scheme combining the Razor principle with stoppable clocks in a GALS setting. This scheme avoids any timing failure due to metastability and does not require any checkpointing or pipeline restarting logic, other than the usual auxiliary latch to store valid data. The experiments show how the Razor principle can be extended to any generic logic circuit, and not just to microprocessors with sophisticated pipeline flush/recovery mechanisms. In this way, the performance/power benefits of Razor can be adopted without the complex architectural changes required by the various Razor schemes in the literature.

A programmable low power current source for bioimpedance measurement: Towards a wearable personalized health assistant.

Bioimpedance is a noninvasive measurement method that facilitates body composition analysis, besides being indicative of many other health parameters. In this work a novel programmable, low complexity, high output impedance, high voltage compliance and wideband current source for bioimpedance applications is presented. Previously, we designed, fabricated and tested in vivo a bio-patch for acquisition of multiple bio-signals. Upon integration with our previous work, this circuit is envisioned to constitute part of a personalized health assistant. Simulation at worst case corners and real operation conditions was carried out using UMC-180 nm 1 poly 6 metal CMOS process. Full duty cycle, shortened or stepped square waves can be generated. Amplitude control of 8 different current levels is supported. Frequency can be tuned up to 1 MHz and an output impedance of 2.8 MO @ 250 KHz is achieved at full current capacity. Total current consumption is comparable to the injected current, making the circuit highly efficient.

A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking

Wide voltage range operation for DSPs brings more versatility to achieve high energy efficiency in mobile applications. This paper describes a 32 bits DSP fabricated in 28 nm Ultra Thin Body and Box FDSOI technology. Body Biasing Voltage (VBB) scaling from 0 V up to ±2 V decreases the core VDDMIN to 397 mV and increases clock frequency by +400%@500 mV and +114%@1.3 V. The DSP frequency measurements show 2.6 GHz@1.3 V(VDD)@2 V(VBB) and 460 MHz@397 mV(VDD)@2 V(VBB). The lowest peak energy efficiency is measured at 62 pJ/op at 0.53 V. In addition to technological gains, maximum frequency tracking design techniques are proposed for wide voltage range operation. On silicon, at 0.6 V, those techniques allow high energy gain of 40.6% w.r.t. a worst case corner approach.

Reference Calibration of Body-Voltage Sensing Circuit for High-Speed STT-RAMs

With the continuing scaling of MTJ, the high-speed reading of STT-RAM becomes increasingly difficult. Recently, a body-voltage sensing circuit (BVSC) has been proposed for boosting the sensing speed. This paper analyzes the effectiveness of using the reference calibration technique to compensate for the device mismatches and improve the read margin of BVSC. HSPICE simulation results show that a 2-bit reference calibration can improve the worst-case read margin in a 1-Mb memory by over 3 times. This leads to up to 30% higher yield across all process corners. In order to maintain the yield improvement even in the worst-case corner, independent calibration circuitry has to be deployed for each memory array.

A complete SPICE subcircuit-based model library for organic photodiodes

A precise model library based on an equivalent circuit is presented and discussed. The model fully describes the light and bias behaviours of organic photodiodes realized on plastic substrates. The sub circuit modelling consists of a single SPICE LEVEL1 diode, a light power dependent series resistance, a shunt resistance. A combined light-power and voltage-controlled current source is also used to emulate the sensitivity behaviour of the photodiode. Moreover the model also permits designers to follow the technology deviations through the inclusion of worst-case corners. Finally a statistical model is included in order to allow designers run Monte Carlo simulations.

Sub-threshold synchronizer

Sub-threshold operation has been proven to be very effective to reduce the power consumption of circuits when high performance is not required. Future low power systems on chip are likely to consist of many sub-systems operating at different frequencies and VDDs from super-threshold to sub-threshold region. Synchronizers are therefore needed to interface between these sub-systems. However, VDD scaling rapidly degrades synchronizers' performance making them unsuitable for sub-threshold operation. For the first time, we analyze the synchronizer performance at ultra low voltages and propose to apply forward body bias to extend the operation of synchronizers to the sub-threshold region and to make them resilient to process variation. We show that applying full-VDD bias significantly increases the transconductance of the bi-stable in synchronizers without adding capacitance to the switching nodes. As a result all the circuit parameters (τ metastability time constant, Td normal propagation delay and Tw metastability window) determining synchronizer performance or mean time between failure (MTBF) can be improved by more than 80% (i.e. by five times) in the sub-threshold region. We also study the impact of process variation on the synchronizer performance in the sub-threshold region and conclude that with full-VDD bias the synchronizer MTBF can be improved from seconds to years for the worst case corner. Finally, we propose an implementation scheme of full-VDD body-biased synchronizer, which is able to work for a wide range of VDDs from sub-threshold region to nominal VDD with nearly zero overhead.

Dual-[formula omitted] assignment policies in ITD-aware synthesis

Traditionally, the effects of temperature on delay of CMOS devices have been evaluated using the highest operating temperature as a worst-case corner. This conservative approach was based on the fact that, in older technologies, CMOS devices systematically degraded their performance as temperature increases.With the progressive scaling of technology, however, there has been a continuous reduction of the gap between supply and threshold voltages of devices, mostly due to low-power constraints. The latter have accelerated this trend by using libraries containing multiple instances of a cell with different ranges of threshold voltages; in particular, the use of high-Vt cells to control sub-threshold leakage currents has made this gap smaller and smaller.The consequence of this trend is the occurrence of the so-called inverted temperature dependence (ITD), under which cells get faster as temperature increases. This new thermal dependence has made the old worst-case design approach obsolete, posing new EDA challenges. Beside complicating timing analysis, in particular, ITD has important and unforeseeable consequences for power-aware design, especially in dual-Vt logic synthesis. Due to a contrasting temperature dependence between low-Vt cells (which enjoy the classical, direct temperature dependence) and high-Vt cells (for which an inverted temperature dependence holds), a single-temperature worst-case design approach fails to generate netlists that are compliant with timing constraints for the entire temperature range.In this work, we first validate the relevance of ITD on an industrial 65nm CMOS multi-Vt library. Then, we describe an ITD-aware, dual-Vt assignment algorithm that guarantees temperature-insensitive operation of the circuits, together with a significant reduction of both leakage and total power consumption. The algorithm has been tested over standard benchmarks using three different replacement policies.Experimental results show an average leakage power savings of 50% w.r.t. circuits synthesized with a standard, commercial flow that does not take ITD into account and thus, to ensure that no temperature-induced timing faults occur, needs to resort to over-design (i.e., over-constraining the timing bound so as to make sure that temperature fluctuations never make the circuits violating the specified required time for all paths).

SICE: design-dependent statistical interconnect corner extraction under inter/intra-die variations

While traditional worst-case corner analysis is often too pessimistic for nanometer designs, full-blown statistical circuit analysis requires significant modelling infrastructures. In this study, a design-dependent statistical interconnect corner extraction (SICE) methodology is proposed. SICE achieves a good trade-off between complexity and pessimism by extracting more than one process corners in a statistical sense, which are also design dependent. Our new approach removes the pessimism incurred in prior work while being computationally efficient. The efficiency of SICE comes from the use of parameter dimension reduction techniques. The statistical corners are further compacted by an iterative output clustering method. Numerical results show that SICE achieves up to 260X speedups over the Monte Carlo method.

Dielectric Reliability for Future Logic and Non-Volatile Memory Applications: a Statistical Simulation Analysis Approach

In this paper, we present a physically-based Monte-Carlo (MC) model reproducing the leakage current flowing across typical dielectric layers (SiO2, high-k) used in ULSI technologies. Simulations will be shown to predict accurately currents measured on MOSFETs, large area MOS capacitor, and tunnel oxides of Flash memories after electrical and radiation stresses. Statistical aspects related to leakage current and threshold voltage are reproduced correctly, allowing worst case corner prediction, necessary to assess dielectric damaging effects on logic circuits and non-volatile memory operation.