Design of low power and low phase noise LC-VCO for Bluetooth/WLAN applications

Abstract

The proposed Inductor-Capacitor Voltage-Controlled Oscillator (LC-VCO) prototype design generates 2.45 GHz to 4.58 GHz of frequency using the Cadence UMC 180 nm process with a 1.8V supply. This architecture carried a new viewpoint on tank design put forth by enhancing the varactor tuning. Here, the circuit employs a CMOS differential cross-coupled pair, and rail-to-rail DC biasing achieves a higher voltage swing. Simulation analysis parameters are measured at 2.45 GHz frequency, phase noise is −123.5 dBc/1 MHz offset, power is 3.5 mW, jitter is 0.232 fsec, and it occupies 0.118 μm2 layout area. Additionally, the simulations have been extended for analysis under Process Voltage and Temperature Corners, Monte-Carlo, and Worst-Case Corners. This study obtained a better FoM of -200.94 dBc/Hz. The simulation results and FoM of the proposed design show a considerably improved than state-of-the-art framework. This LC-VCO circuit study will be suitable for implementing the sub-6 GHz charge pump phase-locked loops (CP-PLLs) system for 5G applications.