Design of robust analog integrated circuit based on process corner performance variability minimization

Abstract

A novel technique of performance optimization along with fabrication process variation tolerance of integrated circuits is proposed in this work. It is well-known that the probability of chip being manufactured under normal process environment is higher than the other corner process environments since it follows a Gaussian distribution. In this proposed approach Process Corner Performance Variability Minimization (PCPVM) is carried out simultaneously with performance optimization. In PCPVM the statistical performance deviations of the corner cases from the nominal case is minimized by considering the actual SPICE (Simulation Program with Integrated Circuit Emphasis) parameters of different process corners for performance evaluation. The proposed design is made robust by optimizing the circuit performance in nominal case and, also minimizing the difference between chip performances in nominal and worst case corner environments. This approach is expected to improve the performance of the ICs manufactured even under extreme process corner conditions. The proposed technique is validated in two example cases of current starved voltage controlled oscillator and Operational Transconductance Amplifier.