Abstract
In this paper, we present a physically-based Monte-Carlo (MC) model reproducing the leakage current flowing across typical dielectric layers (SiO2, high-k) used in ULSI technologies. Simulations will be shown to predict accurately currents measured on MOSFETs, large area MOS capacitor, and tunnel oxides of Flash memories after electrical and radiation stresses. Statistical aspects related to leakage current and threshold voltage are reproduced correctly, allowing worst case corner prediction, necessary to assess dielectric damaging effects on logic circuits and non-volatile memory operation.
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