A non-Monte-Carlo Methodology for Variability Analysis of Magnetic Tunnel Junction Based Circuits

Abstract

This paper presents a non-Monte Carlo (MC) methodology for variability analysis of spin transfer torque magnetic tunnel junction (STT-MTJ)-based circuits. The methodology is implemented by using worst case corner models of STT-MTJ and transistor. The MTJ compact model of worst case corners is proposed for the first time. The design specifications are detailed in non-volatile memory cells and arithmetic unit, e.g., one transistor–one MTJ (1T-1M) memory array, pre-charge sense amplifier (PCSA)-based STT-MRAM and magnetic full-adder circuit. The methodology is implemented by using a 28 nm fully depleted silicon on insulator design kit and this compact model of MTJ. Results show that the proposed methodology is much more efficient than conventional MC method while keeping the same target of performance evaluation. The simulation speed has been improved up to $226\times $ for an effective evaluation of circuit performance (compared with 1000 times MC simulation). MTJ-based circuit designers can assess the impact of process variation on circuit performance without time consuming MC simulations by using this method.