Work Function Of Gate Material Research Articles

Marine predators algorithm for performance optimization of nanoscale FinFET

Fin-shaped Field Effect Transistors (FinFETs) have proved to be an effective solution when transistors are downscaled and conventional MOSFETs do not perform appreciably well in nanoscale regime. The current work emphasizes on the optimization of Rectzoidal FinFET design at shorter gate length and evaluates short channel effects for 20 nm gate length. Various device dimensions like fin width, fin height, equivalent gate oxide thickness, gate material work-function decide the device performance which is, in fact, measured by leakage current, on-current and short channel effects such as Subthreshold swing. Design and simulations for device have been executed in TCAD tool. After simulations, the performance of designed FinFET structure is optimized with the use of marine predators algorithm (MPA), which is an effective optimization technique inspired from foraging strategy opted by ocean predators. A dataset of fin height and fin width acts as input to artificial neural network, which outputs a trained network. Trained network along with the fitness function is inputted to MPA, and optimized output when verified with TCAD results, produces acceptable results. Fitness function tends to reduce the short channel effects and enhance on-current of device. Approximate optimized fin width and fin height values of designed FinFET are 5 nm and 24 nm respectively. This optimized miniaturized device design is appropriate for transistors which are further employed in numerous nanoscale applications.

Performance Characterization of Dual-Metal Triple- Gate-Dielectric (DM_TGD) Tunnel Field Effect Transistor (TFET)

Abstract: Since, Dual Metal Gate (DMG) technology alone is not enough to rectify the problem of low ON current and large ambipolar current in the TFET, therefore, a novel TFET structure, known as dual metal triple-gate-dielectric (DM_TGD) TFET, has been proposed. We have combined the dielectric and gate material work function engineering to enhance the performance of the conventional FET. In the proposed structure, the gate region is divided into three dielectric materials: TiO2/Al2O3/SiO2. This approach is chosen because high dielectric material alone near the source cannot improve the performance due to increase in fringing fields. This paper presents the detail processing of the proposed structure. We have evaluated and optimized the dc performance of the proposed N-DM_TGD TFET with the help of 2-D ATLAS simulator. The results were compared with those exhibited by dual metal hetero-gate-dielectric TFET, single metal hetero- gate-dielectric TFET and single metal triple-gate-dielectric TFET of identical dimensions. It has been observed that the DM_TGD device offers better transconductance (gm), lower subthreshold slope, lower ambipolar current and larger ON current.

Design and Parametric Analysis of GaN on Silicon High Electron Mobility Transistor for RF Performance Enhancement

The need of performance enhancement at the RF and millimeter wave is highly desirable to eliminate the heating effects and power dissipation. Silicon substarte found to be a suitable candidate which reduces about 70% channel temperature than sapphire. To achieve high performance, a GaN on the Silicon substrate high electron mobility transistor is designed and its various performance paramters are analyzed by varying the design specifications. Moreover, the problem of blocking voltage improvement is resolved by epitaxial design approach. Since, threshold voltage, doping-level, work-function of gate material and channel length are considered as some of the important parameters while device modeling. Therefore, the impact of these parameters is examined and analyzed to enehace the performance and reliability of the device for RF applications. The performance parameters like trans-conductance, drain current curves are plotted at different state of device physical and electrical parameters. Results exhibits maximum value of transconductance gm = 13 m-mho, minimum gate capacitance Cg = 0.5pf, wheras Vth is varied between − 0.25 V to 0.25 V.

Simulation and analysis of ZnO- based extended-gate gate-stack junctionless NWFET for hydrogen gas detection

The sensitivity of the hydrogen gas detector can be improved by using the extended-gate technique in nanowire FET. A ZnO-based extended-gate gate-stack junctionless nanowire field-effect transistor (EG-GS-JLNWFET) hydrogen gas device is considered for the first time in this work. Catalytic gate metal, palladium (Pd) on high-K dielectric reduces the overall work function; the concept is further used in sensor design. The presence of gate stacking and extended-gate structure together improve the gate controllability, which results in an improved current ratio. Sensitivity parameters, $${S_{{I_{{{\text{ON}}}} }} }$$ and $${S_{{I_{{{\text{OFF}}}} }} }$$ are considered for performance analysis. Results are compared with JLNWFET. The gate-stack junctionless nanowire field- effect transistor (GS-JLNWFET) shows enhancement compared to both the sensitivities in the proposed device. When compared to JLNWFET-based sensor, EG-GS-JLNWFET shows 2.59% and 24.85% improvement, respectively, in the sensitivity with respect to IOFF and ION for a change of 160 meV in the work function of palladium (Pd). Leakage in any device must be as low as possible, as it lowers the standby power losses in the device. In this work, the proposed design has lowered the leakage as compared to the rest of the two structures. The results also show an augmentation in sensitivity with the increase in gate material work function

Work function optimization for enhancement of sensitivity of dual-material (DM), double-gate (DG), junctionless MOSFET-based biosensor

In this work, the impact of gate material work function on the sensitivity of dual-material, double-gate, junctionless MOSFET ( $$DMDG-JL-MOSFET$$ )-based biosensor has been studied. To enhance the sensitivity of the biosensor, optimization of gate work functions has been done through Sentaurus TCAD simulator. With the immobilization of biomolecules in the cavity at different value of work function of gate metal 1 (M1) and gate metal 2 (M2), i.e., WF1 and WF2, enhancement in sensing metrics (change in threshold voltage $$S_{V{\rm th}}$$ and $$I_{ON}$$ / $$I_{OFF}$$ ratio) is observed. The enhancement in sensitivity is profound in source-side gate (M1) work function (WF1) optimization as compared to drain-side gate (M2) work function (WF2) optimization. Sensitivity of 90 mV is observed in source-side gate work function optimization which is $$\sim$$ 89% more than the sensitivity of 23 mV which is achieved in drain-side gate work function optimization for a fixed concentration and dielectric constant of biomolecules. It has also been noted that the proposed structure exhibits $$\sim 90\%$$ higher sensitivity than the single-material, dual-gate, junctionless MOSFET ( $$SMDG-JL-MOSFET$$ ) biosensor. Results showcase that the optimization of gate metal work functions enhances the sensitivity of the biosensor.

Improvement in electrostatic effeciency using workfunction modulated dual metal gate FinFET

This paper demonstrates a 3-D simulation study of a workfunction modulated dual material gate FinFET (WMDMGF). The source side gate material workfunction of a dual material gate FinFET is modulated linearly keeping drain side material workfunction to be constant. This model provides improvement in terms of DC performance such as better drive current and minimum threshold voltage. Thus, enhancing the switching characteristics of the device and providing better speed. The model is simulated using Silvaco TCAD tool, and the results are compared with single metal gate and dual metal gate FinFET performance.

Robustness to ambipolarity and improvement to HF FOMs of dual-stacked-gate dielectrics underlap heterojunction TFETs

This work presents a new TFET architecture which not only diminishes ambipolar current (IAMB) but also shows high on state current (ION), high ratio of ION to IOFF, and less off-state current (IOFF). Initially, to show the effects on ambipolarity and on- and off-state current, a comparative analysis of transfer characteristics among the proposed, conventional, and the heterojunction (HJ) TFET has been done. The effects of different gate material work functions and gate oxide thicknesses on IAMB for the proposed TFET and the HJ TFET with no underlap are examined. Further, to analyze the effect of ambipolarity in the high-frequency figure of merit (FOM), a comparative analysis on RF parameters such as gate–drain capacitance (Cgd), cutoff frequency (fT), total gate capacitance (Cgg), and the intrinsic time delay (τ) for both of the devices (proposed and HJ TFETs) has been studied.

Drain current modeling of proposed dual material elliptical Gate-All-Around heterojunction TFET for enhanced device performance

Abstract In this paper, analytical drain current modeling of proposed Dual Material (DM) Elliptical Gate-All-Around (GAA) Heterojunction TFET is developed considering depletion regions at both source/channel and drain/channel junctions. Initially, channel potential is derived and is used to calculate the electric field. Based on formulated expression of electric field, a compact drain current model is introduced applying Kane's approach. The device performance is then investigated by varying device parameters including gate material workfunctions, metal length ratios, channel length along with implementation of different gate dielectrics and heterojunction materials to explore its response to channel potential, electric field, drain current and ambipolar characteristics. All the analytical results are compared with Sentaurus simulated data to corroborate our derived model.

A new 2 D mathematical modeling of surrounding gate triple material tunnel FET using halo engineering for enhanced drain current

In this paper, an analytical model is developed for new modified Surrounding Gate Triple Material Tunnel FET with halo doping engineering. The benefits of halo engineering and triple material surrounding gate SG-TFET are incorporated into a novel structure called Surrounding Gate Triple Material Tunnel FET with halo doping (H-SGTMTFET) and has been proposed. A two dimensional analytical model is created by comprehending the Poisson’s equation utilizing parabolic approximation method with appropriate device boundary conditions. The various electrical parameters such as potential, electric field along the channel, vertical direction electric field and drain current of the H-SGTMTFET are derived and analyzed. The performance analysis is done for various gate material work functions and different halo lengths namely 10 nm, 15 nm and 20 nm. It has been found that H-SGTMTFET structure gives very low leakage current IOFF (10−13 A/µm), remarkable improvement in ON current (10−4 A/µm) and the ION/IOFF ratio is 109. Also the ON current (ION) improves by 3 orders of magnitude compared with the Surrounding gate TFET. This new device undoubtedly, proves to be the best alternate for next generation low power and high speed applications. The analytical model has been compared with the simulator TCAD and an excellent conformity is achieved.

Stacked Gate FinFET with Gate Extension for Improved Gate Control

Referring to the experimental data available, a modified pile gate bulk FinFET device with trapezoidal cross-section is analyzed through this paper. Two special features of Pile gate FinFET are trapezoidal cross-section and extended gate. The comprehensive performance metrics analysis justifies its improved performanceas compared to normal bulk FinFET. The device design analysis is also carried out for varying fin height, length of extension of the gate structure and bottom gate material work function. Thermal reliability is justified through analyzing electrical propertied for varying temperatures. The performance metrics considered for the analysis include threshold voltage, transconductance Subthreshold Slope, Drain Induced Barrier Lowering and Gate Induced Drain Leakage current.

Physics-Based Generalized Threshold Voltage Model of Multiple Material Gate Tunneling FET Structure

A generalized 2-D analytical model of gate threshold voltage for multiple material gate Tunneling FET (TFET) structures is derived. The model can also be used for calculating threshold voltage of a single metal gate TFET. Surface potential model of a triple material double gate TFET has been developed by applying Gauss's law in the device. From the potential model, physics-based model of gate threshold voltage has been derived by exploring the transition between linear to quasi-exponential dependence of drain current on applied gate bias. The model includes the effect of gate and drain bias, gate material workfunction, oxide thickness, silicon film thickness, gate dielectric, and other device parameters. The accuracy of the proposed model is verified by comparing the results predicted by the proposed model to the results of the numerical model developed in Silvaco, Atlas.

Performance investigation of bandgap, gate material work function and gate dielectric engineered TFET with device reliability improvement

This script features a study of bandgap, gate material work function and gate dielectric engineering for enhancement of DC and Analog/RF performance, reduction in the hot carriers effect (HCEs) and drain induced barrier lowering (DIBL) for better device reliability. In this concern, the use of band gap and gate material work function engineering improves the device performance in terms of the ON-state current and suppressed ambipolar behaviour with maintaining the low OFF-state current. With these advantages, the use of gate material work function engineering imposes restriction on the high frequency performance due to increment in the parasitic capacitances and also introduces the hot carrier effects. Hence, the gate dielectric engineering with bandgap and gate material work function engineering are used in this paper to overcome the cons of the gate material work function engineering by obtaining a superior performance in terms of the current driving capability, ambipolar conduction, HCEs, DIBL and high frequency parameters of the device for ultra-low power applications. Finally, the optimization of length for different work function is performed to get the best out of this.

Dielectric and work function engineered TFET for ambipolar suppression and RF performance enhancement

A novel approach to suppress the ambipolar behaviour and enhance RF parameters is proposed for the first time. For this, the dielectric and gate material work function engineering is used to suppress the ambipolar behaviour individually. Further, the combination of gate dielectric and gate material work function engineering is used to suppress the ambipolar conduction in huge amount and to eliminate the hot carriers effects. Apart from these, the proposed work improves the ON-state current and RF figures of merit for symmetric devices.

3D simulation of single-event-transient effects in symmetrical dual-material double-gate MOSFETs

Dual-material double-gate (DMDG) structure is a promising structure for future ultra-scaled devices thanks to its capability to reduce short channel effects (SCEs) and hot-carrier induced effects (HCEs). This is due to a step in the surface-potential profile which screens the source side of the channel from drain-potential variations and reduces the drain electric field. In this work, we investigate the DMDG sensitivity to single-event transients. The impact of dual gate material workfunctions on the bipolar gain is particularly addressed. We show that DMDG is naturally less radiation immune than the usual single-material DG (SMDG) devices.

Bias and geometry optimization of FinFET for RF stability performance

This paper presents RF stability of FinFET at particular bias and geometry conditions. The article provides guideline for optimizing the FinFET at RF range. The FinFET geometrical parameters such as gate spacer length, height of silicon fin, and thickness of silicon fin along with gate material work function and bias conditions are adjusted to optimize the device for better stability performance at RF range. The critical frequency (f k ) is obtained for different bias and geometry conditions using numerical simulation. The result shows that the optimized FinFET exhibits good RF stability performance.

An Investigation of Linearity Performance and Intermodulation Distortion of GME CGT MOSFET for RFIC Design

In this paper, an extensive study on the intermodulation distortion and the linearity of gate-material-engineered cylindrical-gate MOSFET (GME CGT MOSFET) has been done, and the influence of technology variations such as channel length and gate material workfunction variations is explored using an ATLAS 3-D device simulator. The simulation results reveal that the GME CGT MOSFET design displays a significant enhancement in the device's linearity and intermodulation distortion performance in terms of the figure-of-merit metrics VIP2, VIP3, IIP3, and IMD3 and the higher order transconductance coefficients gm1, gm2, and gm3. The results are, thus, useful for optimizing the device bias point for RFIC design with higher efficiency and better linearity performance.

Performance Optimization of MOS-Like Carbon Nanotube FETs With Realistic Contacts

To make an exact research into the performance of conventional MOS-like carbon nanotube field-effect transistors (C-CNFETs) with realistic contacts, we studied the effect of Schottky contacts on the performance of C-CNFETs following a detailed analysis of contacting circumstances of C-CNFETs in circuit applications. As the research results show, conventional C-CNFETs suffer from weak subthreshold and off -state performances due to the band-to-band tunneling of holes even with Schottky contacts taken into account. Consequently, device structures based on three novel strategies, viz., an electrostatic doping strategy, a dual-gate-material strategy, and a staircase doping strategy, have been proposed. In addition, the simulation results reveal that these three device structures can improve the device performance of C-CNFETs in the form of steeper subthreshold characteristic, low enough potential off-state current, or (and) monotonic transfer characteristic. At the same time, it should be noted that the performances of these three strategies sensitively depend on the choice of tuning voltage, work function of gate material, or doping concentration of lightly doped source/drain leads, which should be paid with much attention in application.

Two Dimensional Analytical Potential Modeling of Nanoscale Fully Depleted Metal Gate Double Gate MOSFET

In this paper, a 2D analytical potential modeling of nanoscale Double Gate MOSFET is carried out through evaluation of center and surface potential. An analytical expression of 2D potential for asymmetric double gate MOSFET and symmetric double gate MOSFET with ultra thin body (UTB) with the consideration of boundary value approach problem based on the physics of the device has been developed. The center and surface potential model is developed analytically in this paper which is valid below threshold voltage. The post threshold characteristics has been done using ATLAS simulator. Further, in this paper with the proper gate workfunction engineering, we have modeled the 2D potential for midgap semiconductor with workfunction of gate material as 4.61 eV and for Metal Gate Double Gate MOSFET, Hf as a gate metal with buffer layer AIN x with the workfunction of the gate material as 4.4 eV. Quantum corrections are applied for potential modeling as well as threshold voltage modeling. Further, the variation of gate to gate and source to drain potential is carried out. For the purpose of verification and validation of our proposed model, we have compared and contrasted the results obtained through our model and the results obtained through 2D ATLAS device simulator. A close match is obtained between the two, thus validating the approach followed is our analytical model.

Analytical Model of Subthreshold Current and Slope for Asymmetric 4-T and 3-T Double-Gate MOSFETs

In this paper, analytical models of subthreshold current and slope for asymmetric four-terminal double-gate (DG) MOSFETs are presented. The models are used to study the subthreshold characteristics with asymmetry in gate oxide thickness, gate material work function, and gate voltage. A model for the subthreshold behavior of three-terminal DG MOSFETs is also presented. The results of the models show excellent match with simulations using MEDICI. The analytical models provide physical insight which is helpful for device design.

Intermodulation distortion and linearity performance assessment of 50-nm gate length L-DUMGAC MOSFET for RFIC design

The distortion and linearity behaviour of MOSFETs is imperative for low-noise applications and RFICs design. In this paper, an extensive study on the RF-distortion and linearity behaviour of Laterally Amalgamated DUal Material GAte Concave (L-DUMGAC) MOSFET is performed and the influence of technology variations such as gate length, negative junction depth (NJD), substrate bias, drain bias and gate material workfunction is explored using ATLAS device simulator. Simulation results reveal that L-DUMGAC MOSFET significantly enhances the linearity and intermodulation distortion performance in terms of figure of merit (FOM) metrics: V IP2 , V IP3 , IIP3, IMD3 and higher order transconductance coefficients: gm1, gm2, gm3, proving its efficacy for RFIC design. The work, thus, optimize the device’s bias point for RFICs with higher efficiency and better linearity performance.