Wafer Scale Integration Research Articles

Heterogeneous integration of OE arrays with Si electronics and microoptics

This paper describes recent developments of the smart pixel array (SPA) technology for massively parallel optical interconnect applications. Built on Honeywell's commercially successful 850 nm vertical cavity surface emitting laser (VCSEL) technology, the SPA employs a 2D array of VCSELs and photodetectors (PDs). It aims to push optical interconnect density and capacity to a new level, which brings chip-level input and output (I/O) capacity to the order of 100s to 1000s of gigabit per second (Gbps). This technology has several unique features that make it not only technically feasible but also practical for low cost manufacturing. First, it employs an optoelectronic (OE) array based on the new generation of oxide-confined VCSELs that have desired characteristics such as very high speed, high efficiency, and good array uniformity. Second, the OE array has monolithically integrated VCSELs and PDs that provides true bi-directional optical I/O solutions at the chip-scale. Third, it uses hybrid integration techniques such as solder bump bonding and wafer scale integration. The 2D arrays of VCSELs and PDs can be seamlessly integrated with a beam shaping micro-optics array, and with the state-of-the-art Si-based VLSI electronic ICs. Last, and perhaps most importantly, all of the technology implementations follow the guideline of being compatible with mainstream low cost manufacturing practices. Device performance characteristics, integration approach, and prototype demonstration SPA technology up to over 1000 I/O channels per chip are presented, including some early system prototype demonstrations. We believe the SPA technology provides future application specific integrated circuits (ASICs) with new form packaging solutions-a solution that give an ASIC with unprecedented large capacity of very high density and high speed I/Os. It can be used as a new building block to implement varieties of system architectures that are not possible to build with current electrical interconnection.

Vertical and lateral heterogeneous integration

A technique for achieving large-scale monolithic integration of lattice-mismatched materials in the vertical direction and the lateral integration of dissimilar lattice-matched structures has been developed. The technique uses a single nonplanar direct-wafer-bond step to transform vertically integrated epitaxial structures into lateral epitaxial variation across the surface of a wafer. Nonplanar wafer bonding is demonstrated by integrating four different unstrained multi-quantum-well active regions lattice matched to InP on a GaAs wafer surface. Microscopy is used to verify the quality of the bonded interface, and photoluminescence is used to verify that the bonding process does not degrade the optical quality of the laterally integrated wells. The authors propose this technique as a means to achieve greater levels of wafer-scale integration in optical, electrical, and micromechanical devices.

A VLSI array architecture for realization of DFT, DHT, DCT and DST

A unified array architecture is described for computation of DFT, DHT, DCT and DST using a modified CORDIC (coordinate rotation digital computer) arithmetic unit as the basic processing element (PE). All these four transforms can be computed by simple rearrangement of input samples. Compared to five other existing architectures, this one has the advantage in speed in terms of latency and throughput. Moreover, the simple local neighborhood interprocessor connections make it convenient for VLSI implementation. The architecture can be extended to compute transformation of longer length by judicially cascading the modules of shorter transformation length which will be suitable for wafer scale integration (WSI). CORDIC is designed using transmission gate logic (TGL) on sea of gates semicustom environment. Simulation results show that this architecture may be a suitable candidate for low power/low voltage applications.

Efficient and accurate crosstalk prediction via neural net-based topological decomposition of 3-D interconnect

Crosstalk-related issues have become increasingly important with deep submicron downscaling of ICs and wafer scale integration. In today's systems-on-a-chip, the delay through a wire is often greater than the delay through the gate driving it. Furthermore, because of significant parasitic effects, crosstalk between signals on wires can cause major problems. Improved management of the EMI problem is made possible via EDA tools which have the capability of accurately and efficiently modeling electromagnetic interference effects in nanoscale VLSI. However, existing tools are computationally expensive and do not have broad application. The novel methodology proposed in this paper involves topological decomposition of small portions of interconnect (referred to as wirecells) at an extreme level of detail and the creation of parameterized models of these primitive interconnect structures using modular artificial neural networks (MANNs). The technique uses a finite element method program coupled with a circuit simulator and a neural network multi-paradigm prototyping system to produce a library of standard MANN-based wirecell models. It is especially attractive because none of the existing approaches is capable of fully modeling the simultaneous effect on delay and crosstalk of several uncorrelated variables such as interconnect length, width, thickness, separation, metal and insulating medium conductivity and relative permittivity for multiple systems of conductors. The library models derived are used to predict delay noise and crosstalk resulting from interconnect structures embedded in actual analog and digital circuitry.

Development toward an all-silicon integrated thermal management system: the integrated MCM

A new all-silicon multichip module with integrated thermal management system is presented. Our new packaging approach combines the benefits of wafer-scale integration with the flexibility of independently fabricated and pre-tested devices, allowing the development of highly integrated systems. Wet anisotropic etching is used for the dicing of silicon integrated circuits as well as for the fabrication of the chip-receiving cavities in the silicon substrate. The etching exposes {1 1 1} type planes in both chip and receiving surface, assuring a virtually perfect mating of the assemblage. The system is complemented with an integrated silicon heat sink, which can maintain heat fluxes in excess of 100 W/cm2.

Recent developments in application-oriented computer system architectures

This paper describes the different techniques used in the design of efficient application-oriented computer systems. These techniques benefit from the dramatic decline in hardware cost. One main reason for this decline is the new developments in VLSI (very large scale integration), ULSI (ultra large scale integration), and WSI (wafer scale integration) technologies, where it becomes possible to integrate millions of transistors into a single chip. In addition to describing these techniques, a major emphasis is placed on exploring recently developed media processing machines. Such machines meet the requirements of newly developed applications that require sophisticated computational requirements.

Fault-tolerant self-organizing map implemented by wafer-scale integration

The self-organizing map (SOM) implemented by wafer-scale integration (WSI) will provide significantly high speed and desktop-size hardware for many practical applications such as pattern classification, image-processing, and robotics. Due to the synergistic effect of all neurons for ordering, the SOM-WSI is expected to reach the desired global-ordering state even in the presence of defective neurons. This fault tolerant capability, however, has not yet been studied. In this paper, we propose a fundamental SOM-WSI structure and its defect model. From the defect model, we derive a critical-stuck-output and show that if the defective neuron's stuck-output is larger than the critical-stuck-output, the defective SOM can eventually organize itself completely tolerating defects. In an ordinary digital design of a neuron, the critical-stuck-output is proved to be small. Therefore, we can expect high-fault tolerance in the SOM-WSI. Experiments are carried out by injecting defective neurons in a neurocomputer currently used as a prototype of the SOM-WSI. The experimental result agrees well with the proposed theory. In addition, we derive an equation to estimate the degree of fault-tolerance in the SOM hardware by expanding the critical-stuck-output calculation. The derived equation can be used to determine the fundamental design parameters in the SOM-WSI as well as other neurocomputer designs.

Laser formed metallic connections

Solid metallic connections have been successfully formed between two standard levels of metallization using a focused infrared (IR) laser. This new process of laser formed connections has been used to link continuous chains and with resistances of less than 0.8 /spl Omega/ per connection. A commercial laser repair system used extensively by the memory industry was employed to perform approximately 50000 individual links without failure. The electromigration resistance is comparable to standard metal interconnect. This technology has the potential to replace laser fuse cutting techniques to implement repair schemes and it can be used to program wiring in multichip module-deposited (MCM-D) or wafer scale integration applications implemented on silicon substrates. Furthermore, because it is an additive process, it lends itself to redundancy for higher yield and reliability.

IEEE Wafer-scale Integration Conference (WSI'95)

IEEE Wafer-scale Integration Conference (WSI'95)

Fabrication of refractive microlenses in semiconductors by mask shape transfer in reactive ion etching

Refractive microlenses are formed in semiconductor materials by transfer of a lens-like shape of reflowed erodable polyimide mask into the substrate by reactive ion etching. Simultaneous monitoring of the etch rates of the mask material and the semiconductor results in precise control of the lens radius of curvature. We demonstrate wafer-scale integration of GaAs microlenses with vertical-cavity laser diodes and InP microlenses with InGaAs photodetectors. These integrated components can be used directly in optical systems without additional external optics.

ATM switching architectures for wafer-scale integration

This paper proposes the use of wafer-scale integration (WSI) technology for ATM switching systems and presents two different switching architectures specifically designed for WSI. WSI is particularly useful for switching networks since the interconnection lengths are minimized when the entire network is laid out on a single semiconductor wafer. We propose a defect-tolerant multipath buffered crossbar (MBC) with an expandable structure which can easily be scaled up or down according to the choice of wafer size. We also design an ATM-based Manhattan-street network (MSN) as an alternative architecture, suitable for wafer-scale implementation. We compare the two architectures from different standpoints such as performance, defect-tolerance, delay, practicality, testability, complexity, yield, and area.

AREA EFFICIENT LAYOUT OF BALANCED HYPERCUBES

As a multicomputer structure, the balanced hypercube is a variant of the standard hypercube for multicomputers, with desirable properties of strong connectivity, regularity, and symmetry. This structure is a special type of load balanced graph designed to tolerate processor failure. In balanced hypercubes, each processor has a backup (matching) processor that shares the same set of neighboring nodes. Therefore, tasks that run on a faulty processor can be reactivated in the backup processor to provide efficient system reconfiguration. In this paper, we study the implementation of balanced hypercubes in VLSI using the Wafer Scale Integration (VLSI/WSI) technology. Emphasis is on VLSI/WSI layout and area estimates. Our results show that the balanced hypercube can be implemented at least as efficient as the standard hypercube in an area layout and more efficient in a linear layout.

Influence of process parameter variations on the signal distribution behavior of wafer scale integration devices

With decreasing geometries of MOS transistors in VLSI devices, the influence of fluctuations of process parameters during manufacturing will become more and more important, because process tolerances are not proportionally scaled to geometries. These fluctuations result in a performance spread of the devices produced by a certain process. For instance the clock rate of a microprocessor as a typical performance indicator, can vary in a wide range. One of the key issues of the implementation of circuits using wafer scale integration technologies is the synchronous distribution of signals, either clock, data or control over a large area of silicon. Fluctuations of process parameters can have a major influence on the performance of these devices. In the following paper, an efficient method for accurate prediction of the performance spread of integrated circuits is discussed and demonstrated by simulations. All the simulations are verified by measurements on a test-circuit with a huge number of test devices. The method is applied to different signal distribution networks of wafer scale integration devices to show the sensitivity of performance to these variations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Seventh IEEE International Conference on Wafer Scale Integration

Seventh IEEE International Conference on Wafer Scale Integration

Modeling the reliability of a class of fault-tolerant VLSI/WSI systems based on multiple-level redundancy

A class of fault-tolerant Very Large Scale Integration (VLSI) and Wafer Scale Integration (WSI) schemes, called the multiple-level redundancy, which incorporates both hierarchical and element level redundancy has been proposed for the design of high yield and high reliability large area array processors. The residual redundancy left unused after successfully reconfiguring and eliminating the manufacturing defects can be used to improve the operational reliability of a system. Since existing techniques for the analysis of the effect of residual redundancy on reliability improvement are not applicable, we present a new hierarchical model to estimate the reliability of the systems designed by our approach. Our model emphasizes the effect of support circuit (interconnection) failures on system reliability, leading to more accurate analysis. We discuss two area prediction models, one based on the regular WSI process, another based on the advanced WSI process, to estimate the area-related parameters. This analysis gives an insight into the practical implementations of fault-tolerant schemes in VLSI/WSI technology. Results of a computer experiment conducted to validate our models are also discussed.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A silicon VLSI optical sensor for pattern recognition

We show a silicon integrated circuit optical sensor with a high degree of built-in computational power that enables the sensor to recognize specific, preset complex images projected onto its surface. The sensor consists of a multilayer feedforward network, of which the first layer detects local orientations of line and edges. The second layer of this computational sensor recognizes specific configurations of these line and edge orientations. The circuit designs have been kept simple in order to fit within the spaces between the photoreceptors. The design methodology, including that used to set the first and second layer weights, and results from test ICs are shown. The net benefit of such an approach is very high computational density of the order of 2×10 10 weights/cm 2 /s. The approach is very fault tolerant and will permit true wafer scale integration.

3D-WASP devices for on-line signal and data processing

While hybrid and monolithic Wafer-Scale Integration (WSI) technologies have brought about dramatic improvements in the density of integration of embedded massively parallel computers (MPCs), systems and applications engineers continue to demand ever more processing power in less space. The emerging technology of 3D-WSI offers a way of meeting this challenge, giving the potential for step-function increases in parallelism using existing WSI package options. It also permits independent scaling of I/O, parallel processing power and control, leading to a degree of cost-effectiveness that conventional 2D-WSI cannot match. The paper explores the potential of 3D-WASP (WSI Associative String Processor) and reports the results of a study into the engineering feasibility of such a device. This study suggests that a single 3D-WASP device, packages in a standard 2.5"/spl times/2.5"/spl times/0.25" can could deliver 100 Giga-OPS performance form 65536 processing elements, provide up to 64 input-output data channels of 16 bits each and dissipate only 25 W.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The WASP3 monolithic-WSI massively parallel processor

The ASP (Associative String Processor) is a massively parallel fault tolerant associative processor designed for the implementation of extensible parallel processing systems. This paper describes the WASP3 processor, which is an implementation of an ASP processor array, comprising a large monolithic silicon device (5.5 cm/spl times/5.5 cm) hybridized with a bonded-silicon High Density Interconnect (HDI), which has been developed to provide a reliable interconnection medium for Wafer Scale Integration (WSI) devices. The HDI supports multi-layer, passive interconnect, providing superior electrical and noise properties for the distribution of power and signal, and allowing the WSI device to achieve improved logic density by reducing monolithic tracking overheads.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Bit-serial CORDIC DFT computation with multidimensional systolic processor arrays

It is shown how two square arrays, each comprising square root N* square root N CORDIC (Coordinate Rotation Digital Computer) processing elements (PEs), can be used to carry out an efficient two-dimensional (2-D) implementation of the N-point discrete Fourier transform (DFT), with O( square root N) time-complexity, producing N DFT coefficients every square root N time-steps, with fully systolic operation. Generalization to a multidimensional (m-D) solution is also discussed. The CORDIC PE is implemented in bit-serial form, being thus extremely efficient, in terms of speed/area product, and possessing simple interconnects. These characteristics facilitate the mapping of potentially thousands of such units, and hence of entire medium/large DFT modules, onto a single chip, when implemented with very-large-scale-integration (VLSI) or wafer-scale-integration (WSI) technologies. >

Reliable and fast reconfigurable hierarchical interconnection networks for linear WSI arrays

A self-pruning binary tree (SPBT) interconnection network architecture that tolerate faults in a wafer scale integration (WSI) environment is proposed. The goal of the SPBT network is to provide a reliable and a quickly reconfigured interconnection network architecture for linear WSI arrays. The proposed architecture uses a bottom-up approach to reconfigure a linear pipelined array on a potentially defective WSI array using a binary tree interconnection scheme. The binary tree is generated by successive formation of hierarchical modules. For N processing elements (PEs) on the wafer, reconfiguration time is O(log N). The propagation delay is bounded by Theta (log N) and is independent of the number of faulty PEs. Faults in the switching network as well as faulty processing elements are tolerated. >