Abstract
While hybrid and monolithic Wafer-Scale Integration (WSI) technologies have brought about dramatic improvements in the density of integration of embedded massively parallel computers (MPCs), systems and applications engineers continue to demand ever more processing power in less space. The emerging technology of 3D-WSI offers a way of meeting this challenge, giving the potential for step-function increases in parallelism using existing WSI package options. It also permits independent scaling of I/O, parallel processing power and control, leading to a degree of cost-effectiveness that conventional 2D-WSI cannot match. The paper explores the potential of 3D-WASP (WSI Associative String Processor) and reports the results of a study into the engineering feasibility of such a device. This study suggests that a single 3D-WASP device, packages in a standard 2.5"/spl times/2.5"/spl times/0.25" can could deliver 100 Giga-OPS performance form 65536 processing elements, provide up to 64 input-output data channels of 16 bits each and dissipate only 25 W.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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