Wafer Level Reliability Research Articles

Protected Wafer Level Chip Scale Packaging (P-WLCSP)

With the advent of bumped die, new IC packages evolved: for low IO WLCSP (wafer level chip scale package), for high IO FC (flip chip), CBGA (ceramic ball grid array), and PBGA (plastic ball grid array). For low IO, protected CSP is an emerging and rapidly growing market. In 2020 the market exceeded $2B and is ramping to a forecast $2.5B by 2025.1 Initially WLCSP, also known as FI (fan in), was built on the wafer with no active side protection, evolving to single sided protection from a package built on the wafer3 , which transitioned to redistribution PSB (passivation stress buffer)4 . PSBs were implemented in FC wafers for high IO BGA packages. These provided acceptable performance initially, however as devices became more complex and reliability requirements increased, these processes no longer provided the required reliability. To attain higher IO capability and better reliability, performance evolved to CSP5 (non-WL) which allowed larger area for bump distribution and additional protection to the rest of the exposed die surfaces. An example of fully protected die CSP (without substrates or leadframes) encapsulated in mold compound is M-series utilizing a FO (fan out) processes and eWLB.6,7 To obtain higher reliability 6-sided die protection afforded by FO processes require die reconstitution, expensive tapes, molding, and other operations which can feasibly be eliminated in a WLCSP protected FI process assuming full encapsulation can be attained on the original device wafer. American Semiconductor’s Semiconductor-on-Polymer (SoP) 300mm SoP-TM, a P-WLCSP process, is an advanced packaging process optimized for protected fan-in. SoP-TM produces the thinnest and lowest cost fully protected FI. Protected FI process innovations can improve performance in power devices, RF switches, die stacking and thin board applications. This paper includes background on the evolution of CSP, comparison of SOTA (state of the art) FI processes including SoP-TM and builds on low-cost wafer level adaptive process works and reliability data presented on the new SoP-TM process earlier this year.8,9 First article electrical reliability test data for P-WLCSP, adaptive processing of micro-bump pads, and potential applications in hybrid modules will be shown.

A Novel Evaluation Methodology for the Reliability and Lifetime of 200 mm E-Mode GaN-on-Si Power HEMTs

In this paper, a novel evaluation methodology for the reliability and lifetime of E-mode AlGaN/GaN HEMTs has been proposed. A practical example of reliability evaluation is presented for commercial 100V E-mode GaN-on-Si power HEMTs, which are fabricated on an industrial 200mm Si CMOS compatible technology platform. Firstly, wafer-level reliability test (WLRT), Joint Electron Device Engineering Council (JEDEC) qualification and dynamic high temperature operating life (DHTOL) test of 200mm GaN-on-Si power HEMTs for mass production have been carried out. Secondly, the relationships of WLRT with JEDEC and DHTOL have been found, therefore, a fast evaluation method for the reliability of commercial 100V E-mode GaN-on-Si power devices has been established. Finally, DHTOL and switching accelerated lifetime test (SALT) have been carried out to demonstrate the validity of the fast evaluation method. In summary, it is proved that the novel evaluation methodology can better screen the robust GaN power devices, and greatly simplify the reliability testing flow of commercial 200mm GaN-on-Si power devices for mass production.

On the Interpolation from Transistor Figures of Merit to Compact Model Parameters

Circuit simulations are an important step in the verification process of integrated circuits during design projects. They employ compact models that describe the behavior of integrated transistors depending on technology details, geometry, bias conditions (voltages), etc. The parametrization of these models is a complex task and requires expert knowledge. Microscopic wear-out mechanisms cause the behavior of integrated transistors to change over time. By applying over-stress conditions to test transistors, these changes in the behavior can be observed in lab experiments, and they are typically described in terms of wafer level reliability models.Aging simulations investigate the effect of shifts in the transistor behavior on the performance of an integrated circuit in its operating life. To this end, degradation models have to be established to transfer the observed changes in the transistor behavior into shifts of compact model parameters.In this paper, we present an interpolation approach to perform this task based on wafer level reliability models for the changes in the device behavior, as well as further aspects of mapping the observed behavior onto compact model parameters.

Effect of Phosphorus Doped Poly Annealing on Threshold Voltage Stability and Thermal Oxide Reliability in 4H-SiC MOSFET

We have investigated the effect of high temperature annealing of phosphorus doped poly on gate oxide integrity and device reliability. In NMOS capacitance analysis, unstable flat band voltage characteristics and lower oxide breakdown electric field were observed in wafers which received high temperature poly annealing at 1100 °C. Gate oxide integrity (GOI/Vramp) tests and time dependent dielectric breakdown (TDDB) tests were performed to evaluate wafer level reliability. Degraded GOI characteristics and poor gate oxide lifetime were obtained for the high temperature poly annealed condition. To evaluate package level reliability, high temperature gate bias (HTGB) stress tests were conducted. Some samples failed in positive gate bias stress and more severe negative threshold voltage shift was observed in negative gate bias stress for the high temperature poly annealed condition.

An Extended Building-In Reliability Methodology on Evaluating SRAM Reliability by Wafer-Level Reliability Systems

Advancement in integrated circuit (IC) brings a series of challenges on product reliability. In order to meet these challenges and fulfill customers’ requirements, we introduced the methodology of building-in reliability (BIR) into whole stages during IC manufacturing. The wafer-level reliability (WLR) is an essential element of the BIR system. Significant amount of costs, resources, and times are saved from the early detections on reliability deficiencies at design and development stages. After successful mass production, hidden reliability risks can also be timely identified before shipment. Currently, the process reliability has been successfully evaluated by WLR platform. However, the product reliability, which covers much wider reliability factors, has not been effectively covered by WLR. Currently, we still rely on the conventional package-level reliability (PLR) tests to assess product reliability. In this paper, we report how the classical static random access memory (SRAM) is transplanted into the WLR system, which serves as an efficient platform to detect reliability weakness. In our extended BIR methodology, by reasonable test structure and pattern designs, proper electric parameters selections, test methods optimizations, we can thoughtfully consider inherent failure mechanisms and process fluctuations in order to build quantitative reliability models, which are essential to our proposed system. The quantitative reliability model was not seen in the similar WLR approaches and this may explain why these previous proposals failed. Finally, we report the obtained robust correlations between single-bit cell wear-out and package-level SRAM degradations, which is further validated by conventional HTOL tests. Our approaches provide opportunities not only on early detecting reliability weakness, but also on reliability assurance after product deliveries. These two contributions are essential and especially crucial for advanced technology developments.

Performance and Reliability Degradation of CMOS Image Sensors in Back-Side Illuminated Configuration

We present a systematic characterization of wafer-level reliability dedicated test structures in Back-Side-Illuminated CMOS Image Sensors. Noise and electrical measurements performed at different steps of the fabrication process flow, definitely demonstrate that the wafer flipping/bonding/thinning and VIA opening proper of the Back-Side-Illuminated configuration cause the creation of oxide donor-like border traps. Respect to conventional Front-Side-Illuminated CMOS Image Sensors, the presence of these traps causes degradation of the transistors electrical performance, altering the oxide electric field and shifting the flat-band voltage, and strongly degrades also reliability. Results from Time-Dependent Dielectric Breakdown and Negative Bias Temperature Instability measurements outline the impact of those border traps on the lifetime prediction.

The Competing Aging Effects on SRAM Operating Life Tests

The static random access memory (SRAM) is generally used in the technology qualification vehicle (TQV) in the semiconductor industries (e.g., assess process maturity and reliability risks). It is well known that the minimum operating voltage shift ( $\Delta $ Vccmin) will be better if write-dominated is observed, and it will be worse for a read-dominated SRAM. However, in our experiments, a 40-nm technology node TQV SRAM based on the self-timing mechanism, which was read-dominated, showed a reverse outcome. After weeding out most known factors based on an inline, wafer acceptance test (WAT) and wafer-level reliability (WLR) data, we suspected such controversial phenomenon resulted from the competing aging effect of the memory arrays and the peripheral circuits. Through three HTOL experiments, we used the metrics $\Delta $ Vccminw and $\Delta $ Vccminr (i.e., the write and read Vccmin shift) to validate our speculation. The peripheral aging could not be neglected on assessing SRAM reliability, and we might have false conclusions without considering it. It is the first time such competing aging behavior, which easily leads to incorrect assessments, is reported. After successfully identifying the root cause leading to wrong conclusions, we provided a series of suggestions to minimize the impact of the peripheral aging effect and draw the more adequate conclusions. Meanwhile, combined with our experiences, we also provided design guidelines on the TQV SRAM to avoid such “defects” and potential risks.

Voltage-Dependent Activation Energy Maps for Analytic Lifetime Modeling of NBTI Without Time Extrapolation

To enable MOSFETs lifetime extrapolation of up to 10 years, bias temperature instability (BTI) is commonly accelerated via increased stress voltage and increased temperature. We demonstrate that BTI can be described by a unique activation energy map including the voltage and temperature dependence of stress and recovery and use capture and emission time maps to model the time dynamics responsible for the threshold voltage shift of BTI. Based on this approach, we present a new measurement technique, further called temperature-accelerated measure-stress-measurements (TA-MSM) enabling lifetime modeling of BTI without any time extrapolation. We show the application of this technique to simulate standard qualification measurements, fast wafer-level reliability measurements as well as the degradation after ac and dc burn-in stress. In addition, we show that the TA-MSM technique is a valuable tool for the study of the permanent component and the recently discovered reverse recovery effect.

Variation-resilient quantifiable plasma process induced damage monitoring

Many wafer manufacturing processes use plasma or other charge-based effects. The resulting currents can damage or destroy MOS gate oxides of transistors in products. This plasma induced damage (PID) can be in form of a reduction of the required lifetime of the devices, which can result in systematic early product failures in the field. PID damage and the resulting reliability reduction can be invisible in zero hour parameter and product tests, which can make it particularly dangerous.Products have to be made robust against PID by antenna design rules determined during technology development and verified in qualification measurements. To prevent early product fails due to unnoticed process excursions, fast wafer level reliability (fWLR) monitoring on the fully processed product wafer is required. The performance of PID fWLR on suitable test structures and the application of the fast diagnostic stresses will be presented. Details on options for data analysis for fast, sensitive and precise process excursion detection will be discussed based on a set of productive fWLR data following this methodology where false alarms are prevented.For some excursions detected by the fast diagnostic stresses the effect on the device lifetimes will be analysed with long term MOS device stresses. The physical reason for this will be discussed in a simple model of the devices' band structures.

Sub-100 nm2 Cobalt Interconnects

Co has elicited a strong interest to replace Cu for future interconnect applications in microelectronic circuits due to its potentially lower resistivity and better reliability at scaled dimensions. Here, we demonstrate Co wires with electrical cross-sectional areas as small as 34 nm2 using a simple subtractive patterning technique. Semiclassical resistivity modeling of the wire resistivity indicates that grain boundary scattering is the dominant contribution for cross-sectional areas of the order of 100 nm2, while the contribution of surface scattering increases drastically below 50 nm2. Furthermore, wafer-level reliability tests of the Co wires show the high fusing current densities and a strong resistance to thermoelectric stress demonstrating the potential for robust reliability. The resistivity and the reliability of the Co wires are comparable with those of Ru wires.

Influence of Measurement System on Negative Bias Temperature Instability Characterization: Fast BTI vs Conventional BTI vs Fast Wafer Level Reliability

Influence of Measurement System on Negative Bias Temperature Instability Characterization: Fast BTI vs Conventional BTI vs Fast Wafer Level Reliability

A Relaxation Corrected Voltage Ramp Stress Measurement for Fast Wafer Level Reliability

A Relaxation Corrected Voltage Ramp Stress Measurement for Fast Wafer Level Reliability

Early detection and prediction of HKMG SRAM HTOL performance by WLR PBTI tests

With technologies scaling down to 28nm and below, and HKMG (High-κ Metal Gate) process being introduced, the NMOS PBTI (Positive Bias Temperature Instability) becomes a reliability concern due to the higher pre-existing trap density in the HfO2 film. These traps can lead to electron trapping and device parameters shifts. Degradation of Vccmin read is a dominant factor in SRAM Vccmin degradations, and PD (Pull Down) NMOS PBTI degradation dominates the Vccmin read degradation, especially at HKMG development phase because of the un-optimized HK dielectric process. This paper provides a feasible methodology to evaluate chip level HTOL (High Temperature Operation Life) performance based on device level PBTI test by studying a correlation relationship between device Vt degradation in WLR (Wafer-Level Reliability) NMOS PBTI stressed tests and SRAM Vccmin degradation in HTOL tests. The proven correlation model allows characterization of Vccmin shifts in SRAM HTOL through WLR PBTI tests at HKMG development, and therefore has significant impacts in promoting reliability test efficiency and reduces development times.

Plasma process induced damage detection by fast wafer level reliability monitoring for automotive applications

Plasma process induced damage (PID) poses a device lifetime risk to all semiconductor products containing MOS gate dielectrics. This risk increases for smaller technology nodes. In this work we will present how to protect automotive products from PID. Products need to be made robust against PID by design checks with antenna rules determined in technology reliability qualifications. Additionally, damage that is invisible at zero hour, i.e. in parameter or product tests, needs to be detected by fast wafer level reliability (fWLR) monitoring on the fully produced wafer. The application and details of different stress types for charging cases are presented and discussed.

(Invited) Ultra Fine Pitch 3D Interconnects

3D technologies are now in production for high end products. TSV (middle or last) as well as copper pillar have been extensively published over the last few years, specifically for high end memory cubes. Nevertheless, when talking about very high performance systems (HPC or datacenter) or for imaging application (direct stacking of backside illuminated sensor on Logic device), finer pitch technologies are necessary. This paper proposes to enter into details on fine pitch Chip-to-Chip interconnections. More particularly, copper pillar and hybrid bonding technologies will be introduced. Two use cases will then be described; first for HPC application and secondly for high end imager application. 1- Chip-to-Chip interconnection Copper pillars lowest pitch currently available on the market is 40µm. If copper pillar will classically follow the shrinkage trend, the increasing complexity of its integration as well as of the final stacking will make shrink cost prohibitive. Additionally, resistance and capacitance increase due to miniaturization could also discourage designers from using them for advanced partitioning. Thereby, pitch from 20µm to 10µm appear to be the limit. It is one of the reasons why Leti has introduced since few years Cu-Cu hybrid bonding. The latter allowing hermetic bonding without underfill, low resistance and capacitance electrical interconnects and interesting perspectives for ultra-fine pitch. 1.1 20µm pitch copper pillar After introducing the process flow and optimizations required to adapt to fine pitch, a specific focus will be made on critical process steps: impact of barrier and seed layers nature and thickness, lithography, barrier and seed layers etching. Morphological characterization of our 3D interconnects has been achieved through interferometric measurements and FIB/SEM technique. A high uniformity over interconnects height has been obtained at wafer scale. Assembly process including pre-applied underfill will also be deeply described. A test vehicle including daisy chains ranging from 1 to more than 20000 interconnections, has been used to assess process and assembly quality. Electrical tests enable to quickly screen the best assembly configurations. After assembly process optimization, good electrical yields have been obtained and electrical resistance per interconnect is in the range of 45 to 55mΩ. 1.2 Hybrid bonding The hybrid bonding principle will be introduced. The main advantage of this technology is that neither compression nor underfill is needed. Here, fine pitch interconnect is possible thanks to high accuracy equipment. Furthermore, larger pitch application can also take benefit from the process robustness. Last results of wafer level fine pitch technology leading to less than 10µm pitch will be detailed. Extensive electrical data as well as wafer level reliability results are given. A resistance contact around 10mOhms/µm² is obtained. Roadmap and early work on more aggressive pitch (in a perspective of a 2µm to 1µm pitch) are presented. Chip level bonding from its part is based on a similar surface preparation. The complexity here comes from die handling after the wafer level surface preparation: dicing, plasma and chip-to-wafer bonding itself. Process flow will be detailed and daisy chain vehicle test will be described. Electrical data per interconnection show that resistance is very similar to the one obtained at wafer level scale. 2 – Some of potential use cases 2.1 HPC application It is clear now that we are entering the era of zettabytes of information (1021 bytes). For datacenters, the zettabyte era will have to be a “green” computing era. Interposers are key technologies to provide a cost- and power-effective solution. The performances are nevertheless limited in the case of the passive interposer, which only consists in a copper re-routing. To go further, we propose the new concept of “CMOS interposer,” a high-performance but smaller interposer that embeds some logic functions and power management. This concept is only valuable if we have very high density of interconnects from die to die, so through the interposer. Pitch of 20µm was simulated and sufficient considering the whole system, knowing that the interposer embeds 150K interconnections. 2.2 Imager application Stacked imagers, since 2 to 3 years, and more particularly Backside illuminated sensor over logic stack, have been reported by major players in the industry. Connect as nearer as possible pixels to data treatment is a clear advantage of 3D Stack for imaging. Wafer level bonding integration is well suited to this application, as both wafers can be prepared in parallel, their yield are supposed to be good (mature process), top and bottom can be designed to have similar size. A test vehicle will be described and electrical data will be given. Early work on reliability (thermal cycling and electromigration) will be detailed. Figure 1

Fast wafer level reliability monitoring as a tool to achieve automotive quality for a wafer process

This work describes and discusses fast wafer level reliability (fWLR) Monitoring as a supporting procedure on productive wafers to achieve stringent quality requirements of automotive, medical and/or aviation applications. Examples are given for the various reliability topics: dielectrics, devices, metallisation, plasma charging with respect to required test structures, stress methods and data analysis. Application areas of fWLR are highlighted and limitations considered. Further aspects such as relevant reliability parameters, sampling strategies and out of control action plans are discussed.

SHORT LOOP ELECTRICAL AND RELIABILITY LEARNING FOR THROUGH SILICON VIA (TSV)MID-WAFER FRONT-SIDE PROCESSES

Even as unit processes for high aspect ratio (HAR) through silicon via (TSV) mid-wafer front-side processing are becoming relatively mature, scaling of the TSVs and reduction of cost of ownership (COO) drive significant innovations in processes, equipment and materials. To assess their high volume manufacturing (HVM) worthiness, any new unit processes need to be evaluated with respect to yield, reliability and COO. Fully integrated product runs tend to be too slow and expensive for this purpose. At SEMATECH, we use TSV mid-wafer short loop test vehicles for rapid learning cycles through in-line electrical test (ILT) and wafer-level reliability assessments using voltage ramp dielectric breakdown (VRDB). These test vehicles contain 5 × 50 μm or 2 × 40 μm TSV comb test structures, which are testable after the first front-side metal line layer level. Novel unit processes by our associate member companies are inserted into the process flow, and are optimized and assessed using split lot experiments. Processes including TSV etch, post TSV etch cleans, dielectric liner deposition, Cu diffusion barrier and seed deposition, as well as TSV fill by Cu electrochemical deposition (ECD) were evaluated. ILT and VRDB results for short loop lots are presented and discussed.

Wafer-level reliability characterization for wafer-level-packaged microbolometer with ultrasmall array size

For the development of a small and low-cost microbolometer, wafer-level reliability characterization techniques for vacuum-level packaged wafers are introduced. Amorphous-silicon-based microbolometer-type vacuum sensors fabricated on an 8-inch wafer are bonded with a cap wafer by using an Au–Sn eutectic solder. Membrane deflection and integrated vacuum sensor techniques are independently used to characterize the hermeticity at the wafer level. For a packaged wafer with a membrane thickness below 100 μm, it is possible to determine the hermeticity via a screening test performed using an optical detector. An integrated vacuum sensor having the same structure as a bolometer pixel shows a vacuum level below 100 mTorr. All steps from the packaging process to the fine hermeticity test are implemented at the wafer level to verify that high-volume and low-cost production of the microbolometer is possible.

Evaluation of Polymer Core Solderballs for Wafer Level Reliability Improvements

Nearly half a century ago the first die bumping was developed by IBM that would later enable what we call Wafer Level Packaging. It took nearly 40 years for Wafer Level Chip Scale Packaging (WLCSP), with all of the “packaging” done while still in wafer form to come into volume production. It began with very small packages having solderball counts of 2–6 I/Os. Over the years, the I/O count has grown, but much of the industry perception has remained that WLCSPs are limited to low I/O count, low power applications. But within the last few years, there have been growing demands for WLCSP packages to expand into applications with higher levels of complexity. With the ever increasing density and performance requirements for components in mobile electronic systems, the need has developed for an expansion of applicability for Wafer Level Package (WLP) technology. Wafer Level packaging has demonstrated a higher level of component density and functionality than has been traditionally available using standard packaging. This has led to the development of WLCSPs with larger die and increasing solderball connectivity counts. Development activity has been ongoing for improved materials and structures to achieve the required reliability performance for these larger die. For this study, we have evaluated several different metallic structures used for polymer core solderballs with two different WLCSP structures. The WLCSP structures which were evaluated included a standard 4-mask design with redistribution layer (RDL), using a Polymer 1, Metal RDL, Polymer2, and Under Bump Metallization (UBM); as well as a 3-mask design with RDL, using a Polymer 1, Metal RDL, and Polymer 2. In the first case, the solderballs are bonded to the UBM, while in the second case the balls are bonded to the RDL, using the Polymer 2 layer as the solder wettable defining layer. All of the combinations are tested using the standard JEDEC Temperature Cycling on Board (TCOB) and Drop Test (DT) methodologies. The two different metallurgies of the polymer core solderballs appear to react differently to the two different WLCSP structures. This suggests that the polymer core solderball compositions may perform best when optimized for the specific WLCSP structures that are manufactured. We will review the results of the impact of the different polymer core metallurgies on the TCOB and DT reliability performance of the WLCSPs, showing the interactions of these materials with the two WLCSP structures.

Effectiveness of wafer level test for electromigration wear out reporting in advanced CMOS interconnects reliability assessment

Electromigration (EM) copper lines reliability is assessed through standard wafer level (WL) and PL (PL) test in the present work. Since these tests are highly accelerated, one of the main questions as in all reliability studies is the effectiveness of reporting failure phenomena as they occur under use conditions. WL is known to have been intensively used for fast EM process monitoring on high volumes with elevated stress conditions. On the other hand, the PL test having less aggressive stress conditions is used in a process qualification scheme. We use the later in this study as a reference to evaluate WL test results through various processes. Thus, the present paper deals with the ability of WL in comparison to PL to effectively report reliability performances variations for different Cu lines process modifications. Results from WL reliability and PL reliability are compared in terms of lifetime variations and standard deviation evolution. Only limited correlation is found, suggesting that the failure mechanisms acting for both methods are not the same. Moreover, the results of this study highlight the need of defining new reliable EM testing structures and methods compatible with high volumes monitoring.