SHORT LOOP ELECTRICAL AND RELIABILITY LEARNING FOR THROUGH SILICON VIA (TSV)MID-WAFER FRONT-SIDE PROCESSES

Abstract

Even as unit processes for high aspect ratio (HAR) through silicon via (TSV) mid-wafer front-side processing are becoming relatively mature, scaling of the TSVs and reduction of cost of ownership (COO) drive significant innovations in processes, equipment and materials. To assess their high volume manufacturing (HVM) worthiness, any new unit processes need to be evaluated with respect to yield, reliability and COO. Fully integrated product runs tend to be too slow and expensive for this purpose. At SEMATECH, we use TSV mid-wafer short loop test vehicles for rapid learning cycles through in-line electrical test (ILT) and wafer-level reliability assessments using voltage ramp dielectric breakdown (VRDB). These test vehicles contain 5 × 50 μm or 2 × 40 μm TSV comb test structures, which are testable after the first front-side metal line layer level. Novel unit processes by our associate member companies are inserted into the process flow, and are optimized and assessed using split lot experiments. Processes including TSV etch, post TSV etch cleans, dielectric liner deposition, Cu diffusion barrier and seed deposition, as well as TSV fill by Cu electrochemical deposition (ECD) were evaluated. ILT and VRDB results for short loop lots are presented and discussed.