TSV and Cu-Cu direct bond wafer and package-level reliability

Abstract

A comprehensive study of reliability failure modes in an advanced through-silicon via (TSV) mid process flow is presented in Part I of this paper. This is the first time unique TSV mid reliability failure modes at leading-edge TSV dimensions have been observed and reported. TSV Kelvin, comb and chain test structures with 10:1 aspect ratio and a TSV diameter of 5.5 μm are manufactured using a state-of-the-art TSV process. Through standard BEOL reliability testing and physical failure analysis, we observe that the dielectric and barrier layers close to the bottom of the TSV and the TSV redistribution layer (RDL) interface emerge as the main sources of failures. Voltage ramp dielectric breakdown (VRDB) is compared with time-dependent dielectric breakdown (TDDB) measurements. It is found that VRDB correlates well with TDDB and can serve as a fast method for evaluating process changes or as an in-line process monitor. Copper-to-copper direct bonding (CuDB) is the leading candidate for ultra-high density chip-to-chip interconnects in 3D stacked ICs, because it has the potential to match leading-edge TSV pitches. It is important to consider the reliability aspects of the combined TSV and CuDB interconnect system in a package context. Part II of this paper reports on the design of a TSV and CuDB chip-package interaction test vehicle and first reliability results of the TSV/CuDB combined interconnect.