Interview

Abstract

Dr Dingyou Zhang of GLOBALFOUNDRIES talks about her research interests and the paper ‘BMD Impact on Silicon Fin Defect at TSV Bottom’, page 954. Dr Dingyou Zhang As the semiconductor industry strived to scale according to Moore's Law, the conventional planar ICs encountered many physical, technological and economic bottlenecks. 3D integration technology, by stacking and connecting function blocks in a vertical fashion, promises to alleviate such bottlenecks and has been widely investigated in recent years. The potential benefits of 3D integration include multi-functionality, increased performance, increased data bandwidth, reduced power, small form factor, reduced packaging, increased yield and reliability, flexible heterogeneous integration, and reduced overall costs. Performance improvement in 3D ICs is mainly due to reduction of interconnect length reducing interconnect delay and power consumption. Small form factor is achieved by stacking active device layers on top of one another. During my M.S. and Ph.D. I was working on several research topics related to 3D integration, including TSV thermal-mechanical reliability and a novel chip-to-wafer 3D integration approach. I joined GLOBALFOUNDRIES in 2013 and I am currently working on advanced packaging technologies in the office of the CTO, focusing on through-silicon via (TSV) technology. The TSV is an important enabling component in 3D integration; electrically connecting multiple strata of ICs using short vertical vias that pass through a thinned silicon wafer substrate in order to establish a connection between the active side and backside of the die. Compared to conventional wirebonding and flipchip stacking, TSVs enable high-performance, high functionality, compact heterogeneous systems with high data bandwidth and speed, and low power requirements by providing the shortest interconnect path and higher interconnect density, compactly. However, it is challenging to fabricate reliable TSVs and substantial research is being conducted on aspects including their design, processing materials, metrology development and thermal-mechanical reliability. We report a recently found silicon fin defect at TSV bottom which was identified as a killer defect. To examine the root cause of this defect, we explored different inspection options and finally developed an effective method to catch the defect post TSV deep reactive ion etch. This is compatible with inline inspection and can be easily verified by cross-sectioning the via. With this well-established inspection approach, we were able to further investigate various potential root causes of the defect, such as TSV density microloading, TSV location and photoresist residue impacts. After ruling out other effects, bulk micro defect (BMD) turned out to be a key root cause; based on both BMD simulation and experimental results. Thus a low BMD or non-BMD silicon substrate is recommended to reduce or eliminate this defect. The work provides a viable way to clear this roadblock for TSV manufacturability. This is a killer defect which is hard to detect due to its deep location at the bottom of high aspect ratio vias, it can cause yield loss and requires elimination. We have seen mechanical failures caused by this defect after assembling TSV chips. One example we show is a silicon fin defect at TSV bottom causing copper diffusion into silicon cracks in TSV vicinity, after wafer thinning and TSV backside reveal process. A desirable inspection point for using our SEM automatic process inspection is right after TSV etch. Post etch is the first step in which we found this silicon fin defect and it saves downstream manufacturing resources from processing defective TSVs. Post etch inspection results can be easily verified physically and correlated to silicon fin defects, since TSVs are not filled with metal yet. This inspection approach can be adopted after TSV etch and before photoresist ashing and clean, which has less Q time concerns than between TSV post etch clean and dielectric liner deposition. 3D integration is predicted to be a key technology to solve performance and cost problems of conventional IC fabrication in the ITRS roadmap, which will probably be based on TSV technology. Full 3D process flows have already been demonstrated with no major showstoppers from a design or process point of view. While cost reduction is still on the to-do list for high volume production, multiple equipment and material suppliers are focusing on optimising processes to lower costs. With a positive outlook for commercialisation, a strong demand for such future 3D IC applications including memories and processors is expected in the next few years.