Wafer Level Reliability Research Articles

Light Switched Plasma Charging Protection Device for High-Field Characterization and Flash Memory Protection

Plasma charging damage (PCD) is usually measured by comparing the measurement results of an undamaged reference structure to the results of structures, which intentionally received PCD. If wafer level reliability structures are required, these test structures, including the damage amplifying antenna, have to be small enough to fit into the scribeline. However, when these test structures, usually transistors, become smaller, it is harder to realize damage-free reference structures, since the ratio from pad antenna to gate area will increase. To avoid this effect, protection devices are commonly placed parallel to the gate of the reference transistors. However, most protection devices do not allow high-field measurement or the use of both polarities, which is important for in-depth PCD analysis. A device, which at the same time protects the test structure from PCD and also permits bipolar high-field stress to be applied to the test structure, is shown in this paper. Its usefulness is demonstrated on a realistic test structure and as a protection device for Flash memory cells.

Lead-Free Solder Material and Chip Thickness Impact on Board-Level Reliability for Low-K WLCSP

This paper evaluates the effect of the solder ball material and chip thickness on board-level reliability using low-K wafer-level chip-scale packaging (WLCSP). The composition of the three evaluated solder ball materials includes SnAg <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1.0</sub> Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> , SnAg <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2.0</sub> Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> , and SnAg <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2.6</sub> Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.6</sub> . The chip thickness is ranging from 200, 300, and 775 ¿m. Initially, the high temperature storage and ten-time multiple reflow tests were used as the wafer-level reliability test items. The work uses both the low speed (500 ¿m/s) and the high speed (200 mm/s and 1 m/s) solder ball shear test to compare the shear force, displacement, and fracture energy of the three solder compositions. The high speed shear test result shows the high silver content correlates to small displacement and the low fracture energy. Next, the finite element model was employed to compare the board level chip and solder ball stress for these three different chip thicknesses. The finite element method simulation results indicate the thinner chip implies the preferred thermal fatigue cycles. In addition, the drop test results show the chip thickness of 200 and 300 ¿m improve the drop test performance (81 drops and 88 drops) by 20.9%-31.34% than that of chip thickness of 775 ¿m. Moreover, the chip thickness of 200 and 300 ¿m substantially enhance the thermal fatigue life (665 cycles and 655 cycles) by 81.44%-84.21% than that of chip thickness of 775 ¿m using the SnAg <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1.0</sub> Cu <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.5</sub> . Notably, the experimental results correlate well with the simulation trend. This work provides a design guideline for selecting the favorable solder materials and the chip thickness to obtain the satisfactory board-level reliability of the low-K WLCSP packaging.

Fast Wafer Level Reliability Monitoring: Quantification of Plasma-Induced Damage Detected on Productive Hardware

This paper describes the investigation of a Plasma-Induced Damage (PID) event in the metal stack of an 8-in 130-nm-high volume process line. The relevant PID stress and measurement sequence used during standard productive fast Wafer Level Reliability Monitoring, which had detected this event, is discussed, and it is shown to be very effective. Additionally, hot carrier stress was performed on MOS transistors with antenna structures connected to the gate electrode for the quantification of the effect of PID on MOS device characteristics. It is demonstrated that the complete investigation can be done on production wafers in a very short time and only on scribe line test structures, saving time and hardware cost for extra wafers.

W-plug via electromigration in CMOS process

We analyze the failure mechanism of W-plug via electromigration made in a 0.5-μm CMOS SPTM process. Failure occurs at the top or bottom of a W-plug via. We design a series of via chains, whose size ranges from 0.35 to 0.55 μm. The structure for the via electromigration test is a long via chain, and the layer in the via is Ti/TiN/W/TiN. Using a self-heated resistor to raise the temperature of the via chain allows the structure to be stressed at lower current densities, which does not cause significant joule heating in the plugs. This reduces the interaction between the plug and the plug contact resistance and the time-to-failure for the via chain. The lifetime of a W-plug via electromigration is on the order of 3 × 107 s, i.e., far below the lifetime of metal electromigration. The study on W-plug via electromigraion in this paper is beneficial for wafer level reliability monitoring of the ultra-deep submicron CMOS multilayer metal interconnect process.

USING REVERSE ARRANGEMENT TEST TO DETECT NON-MONOTONIC TRENDS FOR SEMICONDUCTOR MANUFACTURING AND RELIABILITY TESTS

The limitation of the trend test in SPC is reviewed. The current Nelson's run test for the six or seven consecutive increasing or decreasing points cannot detect non-monotonic increasing or decreasing trend that is frequently encountered in industries. This paper proposes the reverse arrangement test (RAT) to replace the current SPC trend test rule in order to detect both non-monotonic and monotonic increasing or decreasing trends. The theory of RAT is reviewed and we point out the errors in the tables from a well-known and most frequently referenced paper on RAT. The corrected tables of accumulated probabilities for each total reverse arrangement for N = 3 to 12 are presented. The false alarm rate from RAT is verified with excellent accuracy by 108data points simulating stable normal distributed process. Real examples from the semiconductor manufacturing illustrate that 7 non-monotonic increasing points can be detected by RAT with the same false alarm rate as for the 6 monotonic increasing trend, while sometimes none of the current WECO and Nelson's rules can detect such abnormal pattern. Applications of RAT in IC SPC and WLRC (Wafer Level Reliability Control) show RAT is much more powerful than conventional monotonic trend tests in detecting nonconformance.

Electromigration Reliability Assessment of Cu-based Metallization Systems by a Wafer-Level Approach

Recently, a fast improved isothermal method (ISOT) has been devised to characterize the electromigration (EM) wafer level reliability (WLR). In this paper, the usefulness of ISOT will be shown, not only for the aim of process monitoring in production, but also, when the method is applied carefully, to complement and, in perspective, to substitute the expensive standard package-level reliability (PLR) tests, currently used to assess the EM reliability. The complete methodological approach is described, as well as precautions to control the stress conditions and normalization procedures to account for the process parameter spread. Some results on double-damascene 90 nm Cu technology are shown.

From wafer-level gate-oxide reliability towards ESD failures in advanced CMOS technologies

The impact of a short-term electrical overstress on dielectric reliability is thoroughly investigated using a dedicated experimental equipment for measurement times in the millisecond and microsecond range. Based on significant statistics, it is confirmed that the dielectric stress-induced damage is cumulative in nature. In addition, the voltage acceleration is shown to follow the power-law model towards the time range of electrostatic discharge and furthermore the breakdown statistics remain unchanged. These results justify the assessment of a short-term electrical overstress in advanced CMOS technologies by using a conventional reliability prediction methodology.

A Versatile, Via Terminated Electromigration Test Structure for Various Stress Modes Used During Fast Wafer Level Reliability (fWLR) Testing

A multipurpose electromigration (EM) test structure designed for advanced fast wafer level reliability (WLR) tests is described in this work. It is shown that different failure location and failure modes can be detected electrically by this test structures which is beneficial for early technology development as well as productive in-line monitoring. Highly accelerated WLR tests use the metal self-heating effect for temperature stress acceleration. It is shown here that the design of interconnects with respect to the critical metal line and the periphery of the tested metal line has a large impact on the stress temperature. A carefully designed test structure guarantees the ability to test for different EM failure modes (upstream, downstream). The presented experimental data focuses on the investigation of different process splits.

Wafer level reliability and lifetime analysis of InGaAsP/InP quantum-well Fabry-Perot laser diode

This paper investigated the reliability of semiconductor 1.3-/spl mu/m multiquantum-well (MQW) Fabry-Perot laser diodes (LDs) in a quarter 2-in wafer level that are measured to have uniform threshold currents, slope efficiencies, and wavelengths within 4% of the maximum deviation. By performing the accelerated aging test under a constant optical power of 3 mW at 85/spl deg/C for 2100 h, the lifetime of the fabricated optoelectronic devices was estimated, where the failure rate was matched on the fitted line of the lognormal distribution model resulting in the mean-time-to-failure (MTTF) of 2/spl times/10/sup 6/ h operating at room temperature.

Wafer level reliability and leakage current modeling of PZT capacitors

Over the last few years, thin films of PbZr x Ti 1− x O 3 (PZT) have been the focus of extensive researches for high-k capacitor applications. However, some electrical properties such as leakage current conduction and degradation mechanisms need to be better understood. From Constant Voltage Stress experiments, we identified two distinct failure mechanisms depending on the applied voltage levels. The existence of these two failure mechanisms makes it impossible to extrapolate lifetime results from high voltage to low voltage. Since the typical operating voltage for decoupling capacitors is around 3 V the reliability study has to be focused on the low voltage breakdown. A good opportunity to learn about the low voltage failure mechanisms is to investigate the characteristics of leakage current. The time evolution of leakage current is mainly controlled by the resistance degradation phenomenon. A quantitative analytical model has already been developed to account for this effect. We propose a more complete model that also includes dielectric relaxation and trapping effects. The resulting model is combined to a charge-influenced thermoionic emission model that fits fairly well the voltage and temperature dependence of leakage current. The static and dynamic parts of our model are found to be consistent, especially in terms of barrier lowering effect induced by the resistance degradation process. We believe that the low voltage breakdown is related to a trapping-induced creation of defects in the film.

Chip-packaging interaction: a critical concern for Cu/low k packaging

Chip-packaging interaction is becoming a critical reliability issue for Cu/low k chips during package assembly. With the traditional TEOS interlevel dielectric being replaced by much weaker low k dielectrics, packaging induced interfacial delamination in low k interconnects has been widely observed, raising serious reliability concerns for Cu/low k chips. In a flip-chip package, the thermal deformation of the package can be directly coupled into the Cu/low k interconnect structure inducing large local deformation to drive interfacial crack formation. In this paper, we will first review the experimental techniques for package thermal deformation measurement and interfacial fracture energy measurement for low k interfaces. Then 3D finite element analysis (FEA) based on a multilevel sub-modeling approach in combination with high-resolution Moiré interferometry is employed to examine the packaging effect on low k interconnect reliability. Our results indicate that packaging assembly can significantly impact wafer-level reliability causing interfacial delamination to become a serious reliability concern for Cu/low k structures. Possible solutions and future study are discussed.

Evaluation of performance–reliability trade-offs in a Si–Ge BiCMOS process using fast wafer level techniques

Fast wafer-level reliability (fWLR) techniques are successfully implemented in order to investigate several gate oxide reliability–performance tradeoffs that affect the architecture of a high speed BiCMOS process. Fast feedback of device and reliability parameters is required during process development in order to avoid failures during process qualification. This study highlights some performance–reliability tradeoffs that had to be overcome during the development of a modern BiCMOS process.

Applying the fWLR concept to Stress induced leakage current in non-volatile memory processes

A fast wafer level reliability structure and evaluation method has been developed for stress induced leakage current (SILC) in non-volatile memory processes. The structure is based on parallel floating gate cell arrays. The evaluation method is straightforward, and not time-consuming. The measurement consists of bi-directional FN tunneling stress (to degrade the tunnel oxide and to develop the SILC) and a negative voltage gate stress (to reveal the SILC). An empirical SILC parameter has been defined as the lowest cell V t in the parallel NVM array. This method has been implemented as part of end-of-line measurements in Philips embedded Flash processes, and has been proven to be very effective and powerful in experimental split analysis, process reliability monitoring/control, and process transfers.

An introduction to fast wafer level reliability monitoring for integrated circuit mass production

The continuous verification of process reliability is essential to semiconductor manufacturing. The tool that accomplishes this task in the required short time is the fast wafer level reliability monitoring (fWLR). The basic approaches for this task are described in this introductory overview. It summarizes sampling plans, discusses the feasibility of using fWLR for screening and describes the data assessment and application of control cards. Beyond these general topics many of the fWLR stress methods are described in detail: Dielectric stressing by means of an exponential current ramp is compared to ramped voltage stress. Especially for thin oxides the methods differ regarding the soft breakdown detection and the time they consume. Another task of fWLR is the detection of plasma induced damage, which can be achieved by applying a revealing stress to MOSFETs with antenna. The design challenges of the structures and the test method as well as the data assessment are described in detail. An important section deals with fWLR for interconnects. In this section the appropriate test structures (including thermal simulations) are illustrated and fast electromigration stresses are discussed and the details of standard wafer level electromigration accelerated test (SWEAT) are included. For contacts and vias a simple method to check reliability is presented. Finally the monitoring of device reliability is treated. It is shown that using indirect parameters that correlate well to standard parameters such as the drain current can be beneficial for fWLR. For both, the interconnects and the devices, it is essential to have locally heated test structures in order to keep the stress time low. The detection and verification of mobile ions can also be performed with such a self-heated structure. For the described methods examples are given to illustrate the usefulness.

Quantifying charging damage in gate oxides of antenna structures for WLR monitoring

A new method to quantify the reliability risk for gate oxide with plasma induced charging damage (PID) is established. Based on existing antenna test methodology the quantity of inflicted damage is expressed in a physical meaningful number by means of a simple model applicable for thick oxides (>5 nm). This model takes trap activation, trap filling, detrapping and also traps generation under constant current test condition (“revealing stress”, “diagnostic stress”) into account. For the corresponding development of the measurable external supply voltage with time an equation is derived. Experimental test data from different oxide thicknesses are fitted to this model equation to obtain its main parameters, the cross section values. These cross section values describe the probabilities for the different trap/detrap processes during stress. Cross section values thus found extend published data for lower electric fields to high electric fields necessary for a fast test. The number of plasma induced traps, which was added to the oxide during wafer processing, can now be determined by applying an electron trapping rate (ETR) test method, and combining it with our dynamic trap generation/filling model. The obtained number of PID related traps opens a path to calculate the corresponding reduction of oxide lifetime. Real measurement data are used to illustrate the method and its applicability to fast wafer level reliability (fWLR) monitoring.

Some practical considerations for effective and efficient wafer-level reliability control

In this paper, some practical considerations for effective and efficient wafer-level reliability control (WLRC) are presented. We propose a better solution to replace the previous method by adding a protection diode to avoid process induced charging damage on test structure devices. This work also provides in-depth discussions on WLR Via electromigration (EM), which correlated well with traditional time-consuming package-level tests. In addition, due to the time constraint at WLRC, some real cases are discussed regarding the suitable sampling plan and test structures. These studies are to improve WLRC effectiveness and efficiency, to diagnose reliability concerns, to expedite WLRC failure analyses when out-of-control, and, thus, to facilitate WLRC lot dispositions.

Packaging effects on reliability of cu/low-k interconnects

Chip-packaging interaction is becoming a critical reliability issue for Cu/low-k chips during assembly into a plastic flip-chip package. With the traditional TEOS interlevel dielectric being replaced by much weaker low-k dielectrics, packaging induced interfacial delamination in low-k interconnects has been widely observed, raising serious reliability concerns for Cu/low-k chips. In a flip-chip package, the thermal deformation of the package can be directly coupled into the Cu/low-k interconnect structure inducing large local deformation to drive interfacial crack formation. In this paper, we summarize experimental and modeling results from studies performed in our laboratory to investigate the chip-package interaction and its impact on low-k interconnect reliability. We first review the experimental techniques for measuring thermal deformation in a flip-chip package and interfacial fracture energy for low-k interfaces. Then results from three-dimensional finite element analysis (FEA) based on a multilevel submodeling approach in combination with high-resolution moire/spl acute/ interferometry to investigate the chip-package interaction for low-k interconnects are discussed. Packaging induced crack driving forces for relevant interfaces in Cu/low-k structures are deduced and compared with corresponding interfaces in Cu/TEOS and Al/TEOS structures to assess the effect of ILD on packaging reliability. Our results indicate that packaging assembly can significantly impact wafer-level reliability causing interfacial delamination to become a serious reliability concern for Cu/low-k structures.

A cost-effective wafer-level reliability test system for integrated circuit makers

Wafer-level reliability (WLR) testing receives much attention and becomes a major tool for process reliability qualification and in-line monitoring because WLR can provide real-time results for timely improvements. This in-situ test capability is greatly attributed to an automatic parametric tester for sample handling and data collection/analysis. This paper presents a cost-effective WLR test system for a semiconductor maker (an IDM as well as a foundry). The proposed system consists of flexible and extensible algorithm generation, which helps realize low-cost WLR solutions. The key features of our proposed system include cost-effective instrumentation (i.e., an Agilent 4156C parameter analyzer, a semi-auto, and thermal CASCADE 12751 wafer prober, a pulse generator, and a switching matrix) and the software for interface control and data analysis. Compared with the corresponding automatic test equipment (ATE), our system is capable of measuring electrical characteristics with higher accuracy and a wider temperature range. This leads to significant cost saving, much enhanced tool utilization, and improved flexibility. Its great extensibility is especially important for a wafer foundry, which often suffers test capacity shortage when numerous verifications and qualifications are to be done.

Ramped current stress for fast and reliable wafer level reliability monitoring of thin gate oxide reliability

A ramped dielectric stress measurement, suitable for fast wafer level reliability (fWLR) monitoring, is assessed for thin gate oxide thicknesses down to 2.2 nm. Severe difficulties usually occur for the reliable detection of soft/hard breakdown in a short time interval and due to high direct tunneling currents. These are discussed and an exponentially ramped current stress is introduced tackling the problems. Early oxide fails were covered by a fast voltage ramp carried out before the current ramp. The advantages of the method are highlighted which has already been implemented for fWLR monitoring in high volume production on scribe line structures.

Improvement of poly-silicon hole induced gate oxide failure by silicon rich oxidation

This paper depicts the improvement of poly-silicon (poly-Si) holes induced failures during gate oxide integrity (GOI) voltage-ramp (V-Ramp) tests by replacing plasma enhanced oxidation with silicon rich oxidation (SRO), which is cap oxide on transfer gate serving as a hard mask to selectively form salicide. The SRO was found to be capable of completely removing salicide block etching induced poly-Si holes. With this SRO film deposited on poly-gate, the higher density silicon in cap oxide fills the interface of poly-Si grains and repairs the poly-Si film damaged by source–drain (S/D) implantation. The plasma-induced damage (PID) effect is observed and SRO can also suppress this PID effect and, thus, enhance GOI process margin. This is because PID may be enhanced during plasma poly-Si etching and S/D implantation, which induces the under-layer latent defects and deteriorates the adhesion between poly-grains and oxide. The SRO refraction index, which is 1.56 in this study with maximum silane (SiH 4) in cap oxide furnace, was found to play an important role on eliminating poly-holes. In-line SEM inspections show that poly-Si holes happen at open area such as the GOI test patterns of large bulk area and of poly-Si edge. Therefore, in-line defect inspections, which usually check only cell area, fail to find poly-Si holes. Hence, the in-line GOI monitor is proposed to detect such “hidden” defects. In this paper, we found SRO can successfully eliminate poly-Si holes, which lead to GOI failures, with minimum productivity loss and negligible process costs. Since GOI monitor by V-Ramp test is implemented to detect such reliability failure, wafer-level reliability control is recommended to proactively monitor and improve GOI performance. In order to achieve more stringent reliability targets as technology marches to the 0.10 μm era, we introduce the concepts of build-in reliability to facilitate qualifications and to incorporate related/prior reliability concerns for developing advanced processes.