The Competing Aging Effects on SRAM Operating Life Tests

Abstract

The static random access memory (SRAM) is generally used in the technology qualification vehicle (TQV) in the semiconductor industries (e.g., assess process maturity and reliability risks). It is well known that the minimum operating voltage shift ( $\Delta $ Vccmin) will be better if write-dominated is observed, and it will be worse for a read-dominated SRAM. However, in our experiments, a 40-nm technology node TQV SRAM based on the self-timing mechanism, which was read-dominated, showed a reverse outcome. After weeding out most known factors based on an inline, wafer acceptance test (WAT) and wafer-level reliability (WLR) data, we suspected such controversial phenomenon resulted from the competing aging effect of the memory arrays and the peripheral circuits. Through three HTOL experiments, we used the metrics $\Delta $ Vccminw and $\Delta $ Vccminr (i.e., the write and read Vccmin shift) to validate our speculation. The peripheral aging could not be neglected on assessing SRAM reliability, and we might have false conclusions without considering it. It is the first time such competing aging behavior, which easily leads to incorrect assessments, is reported. After successfully identifying the root cause leading to wrong conclusions, we provided a series of suggestions to minimize the impact of the peripheral aging effect and draw the more adequate conclusions. Meanwhile, combined with our experiences, we also provided design guidelines on the TQV SRAM to avoid such “defects” and potential risks.