A high-density MOS static RAM cell using the lambda bipolar transistor

Abstract

Abstnrcr–Based upon the common-collector lambda bipolar transistor (LBT), which is built with p-well NMOS, and the Parasitic w-n BJT in a CMOS IC, a novel MOS static RAM eelf catled the LBT celf is proposed. In this new cell, the LBT and two poly-Si resistors form a bktable element with a PMOS access transistor. With the minimum feature size F, the optimal cell area of 32 F2 can be reaJized by using the silicide contact and smnlf p-weff spacing. The REAWWRITE operation is simulated. Due to the need of precharging before reading and the rather slow recovery after reading, suitable peripheral circuits should be designed. (a) Compared with dynamic MOS RAM, static MOS random access memory (RAM) has the advantages of simple operation with no refreshing required. However, the static RAM suffers from low packing density which is caused by the complex cell circuitry. This problem becomes more severe as the memory bit capacity increases. Two methods are applied to solve the problem. One is the use of advanced fabrication technologies to reduce the chip area. The other is the use of new devices or circuits for the cell. The latter method is effective since the total cell area usually occupies 60-70 percent of the total memory chip area. Therefore the efforts of searching for a new cell which has high packing density and good speed-power performance have been increased recently [1] -[ 6]. This correspondence describes a new MOS static RAM cell which is constructed by using a negative resistance device called the lambda bipolar transistor (LBT) [71, [81. The proposed new cell, which is called the LBT cell, consists of one PMOS access transistor and one bistable storage element. The storage element is designed by using two poly-Si resistors and one common-collector type n-p-n lambda bipolar transistor, which consists of an NMOS merged with an n-p-n bipolar junction transistor (BJT). Since the PMOS, NMOS, and n-p-n BJT are compactly merged, the LBT cell has the highest packing density among all MOS static RAM cells. Moreover, it gives a good balance between process complexity, operation complexity, and performance. The proposed new static RAM cell circuit is shown in Fig. 1(a) where the BJT Q2 and the NMOSFET Ml form a lambda bipolar transistor [7] -[8 ] as marked by the dashed line, The collector of the LBT is connected to VDD, while the base and the emitter are connected to VDD and ground through poly-Si resistors R 1 and Rz, respectively. This common-collector type of LBT, together with K I and K2, serves as a bistable storage element which is accessed through the PMOSFET lf3. The typical integrated structure of the LBT cell is shown in Fig. 1(b). It may be seen that the p-well in lkfl also serves as the base of Q2 and the source of the lf3. The bistable characteristics of the storage element in the cell can be understood by superimposing the current-voltage