Early detection and prediction of HKMG SRAM HTOL performance by WLR PBTI tests

Abstract

With technologies scaling down to 28nm and below, and HKMG (High-κ Metal Gate) process being introduced, the NMOS PBTI (Positive Bias Temperature Instability) becomes a reliability concern due to the higher pre-existing trap density in the HfO2 film. These traps can lead to electron trapping and device parameters shifts. Degradation of Vccmin read is a dominant factor in SRAM Vccmin degradations, and PD (Pull Down) NMOS PBTI degradation dominates the Vccmin read degradation, especially at HKMG development phase because of the un-optimized HK dielectric process. This paper provides a feasible methodology to evaluate chip level HTOL (High Temperature Operation Life) performance based on device level PBTI test by studying a correlation relationship between device Vt degradation in WLR (Wafer-Level Reliability) NMOS PBTI stressed tests and SRAM Vccmin degradation in HTOL tests. The proven correlation model allows characterization of Vccmin shifts in SRAM HTOL through WLR PBTI tests at HKMG development, and therefore has significant impacts in promoting reliability test efficiency and reduces development times.