Influence of ultra-thin TiN thickness (1.4 nm and 2.4 nm) on positive bias temperature instability (PBTI) of high-k/metal gate nMOSFETs with gate-last process**Project supported by the National High Technology Research and Development Program of China (Grant No. SS2015AA010601) and the National Natural Science Foundation of China (Grant Nos. 61176091 and 61306129).

Abstract

The positive bias temperature instability (PBTI) degradations of high-k/metal gate (HK/MG) nMOSFETs with thin TiN capping layers (1.4 nm and 2.4 nm) are systemically investigated. In this paper, the trap energy distribution in gate stack during PBTI stress is extracted by using ramped recovery stress, and the temperature dependences of PBTI (90 °C, 125 °C, 160 °C) are studied and activation energy (Ea) values (0.13 eV and 0.15 eV) are extracted. Although the equivalent oxide thickness (EOT) values of two TiN thickness values are almost similar (0.85 nm and 0.87 nm), the 2.4-nm TiN one (thicker TiN capping layer) shows better PBTI reliability (13.41% at 0.9 V, 90 °C, 1000 s). This is due to the better interfacial layer/high-k (IL/HK) interface, and HK bulk states exhibited through extracting activation energy and trap energy distribution in the high-k layer.