Wafer Level Packaging Research Articles

Self-regulated parallel process 3-D array microfabrication with metal direct-write

Parallel process direct-write manufacturing of ultrahigh aspect ratio 3-D metal microstructures remains one of the ultimate challenges in 3-D manufacturing. Its development promises novel solutions for high density chip scale packaging and sorting that require precision microscale mechanical and electrical interfaces to microelectronics. Herein, we exploited a self-regulated growth mechanism revealed in the meniscus-confined direct-write electro-deposition to realize the parallel process fabrication of high-density area arrays of ultrahigh aspect-ratio metal microwire structures. We demonstrated the direct-write fabrication of an array of curvilinear metal spirals over 800 μm in height and 50 μm in array spacing, structurally and mechanically appropriate for high density wafer probe testing applications that cannot otherwise be fabricated with any other existing methods.

Study of the Absorption of Electromagnetic Radiation by 3D, Vacuum-Packaged, Nano-Machined CMOS Transistors for Uncooled IR Sensing.

There is an ongoing effort to fabricate miniature, low-cost, and sensitive thermal sensors for domestic and industrial uses. This paper presents a miniature thermal sensor (dubbed TMOS) that is fabricated in advanced CMOS FABs, where the micromachined CMOS-SOI transistor, implemented with a 130-nm technology node, acts as a sensing element. This study puts emphasis on the study of electromagnetic absorption via the vacuum-packaged TMOS and how to optimize it. The regular CMOS transistor is transformed to a high-performance sensor by the micro- or nano-machining process that releases it from the silicon substrate by wafer-level processing and vacuum packaging. Since the TMOS is processed in a CMOS-SOI FAB and is comprised of multiple thin layers that follow strict FAB design rules, the absorbed electromagnetic radiation cannot be modeled accurately and a simulation tool is required. This paper presents modeling and simulations based on the LUMERICAL software package of the vacuum-packaged TMOS. A very high absorption coefficient may be achieved by understanding the physics, as well as the role of each layer.

Packaging design for improving the uniformity of Chip scale package (CSP) LED luminescence

In order to realize small package size, uniform performance and high manufacture efficiency, a chip scale packaging (CSP) technology has been developed by controlling the thickness of the phosphor film in this paper. Five CSP LEDs with different thicknesses of 4 side faces are prepared. Optical tests and thermal simulations were carried out to evaluate the performance of the five samples. The measurement results indicate that: 1) When the absorption of the blue light reached a certain extent, the luminous flux and correlated color temperature gradually decreased with the increase of the thickness of the film; 2) the color temperature of the CSP LED will reach the best uniformity when the ratio of thickness of top film to that of side film is close to 2:1; 3) when the ratio of thickness of top film to that of side film is not less than 2:1, the effective light angle can reach about 160°; 4) the thermal management for prepared CSP samples shows a slight decrease in temperature as the side film's thickness increases; 5) the aging test result shows that the thinner the package thickness is, the stronger the aging resistance will be.

Improved Die Attribute Recognition via Colored Glass Wafer

The rise of various Wafer technologies has been developed based on industries and applications requirement. Highest quality of material characterization is complex and requires specialized process equipment and manufacturing procedures to meet defined design standards. The paper presents distinctive glass wafer-level fabrication technology that will enhance its properties with respect to pattern recognition system (PRS) at back-end manufacturing for industrial applications. Feasibility of colored glass wafer has been built into proposed conception to manufacture wafer-level packaging. The idea from transparent to colored glass wafer came from manufacturing key challenges that cutting sequence during pattern recognition cannot be distinguished. The proposed solution will mitigate high risk of misaligned cut at wafer sawing and its potential attachment on leadframe during die attach. glass wafer dice, transparent in nature, intermittently encountered multiple PRS assist during Wafer sawing and die attach as it hardly recognizes its cutting positions. Since dependent of machine capability limitations, misaligned cut is inevitable and usually happen occasionally. Addressing its unrecognizable characteristic, proposed colored glass wafer and with visible outline and saw lane fabrication was conceptualized instead of seeking ideal and high equipment model that can differentiate its opaque feature. The colored glass wafer and with visible outline and saw lane naturally creates segmentation visibly and will not be parameter dependent during manufacturing.

Deformation Behavior of Various Interconnection Structures Using Fine Pitch Microelectromechanical Systems (MEMS) Vertical Probe.

Recently, fine pitch wafer level packaging (WLP) technologies have drawn a great attention in the semiconductor industries. WLP technology uses various interconnection structures including microbumps and through-silicon-vias (TSVs). To increase yield and reduce cost, there is an increasing demand for wafer level testing. Contact behavior between probe and interconnection structure is a very important factor affecting the reliability and performance of wafer testing. In this study, with a MEMS vertical probe, we performed systematic numerical analysis of the deformation behavior of various interconnection structures, including solder bump, copper (Cu) pillar bump, solder capper Cu bump, and TSV. During probing, the solder ball showed the largest deformation. The Cu pillar bump also exhibited relatively large deformation. The Cu bump began to deform at OD of 10 μm. At OD of 20 μm, bump pillar was compressed, and the height of the bump decreased by 8.3%. The deformation behavior of the solder capped Cu bump was similar to that of the solder ball. At OD of 20 μm, the solder and Cu bumps were largely deformed, and the total height was reduced by 11%. The TSV structure showed the lowest deformation, but exerted the largest stress on the probe. In particular, copper protrusion at the outer edge of the via was observed, and very large shear stress was generated between the via and the silicon oxide layer. In summary, when probing various interconnection structures, the probe stress is less than that when using an aluminum pad. On the other hand, deformation of the structure is a critical issue. In order to minimize damage to the interconnection structure, smaller size probes or less overdrive should be used. This study will provide important guidelines for performing wafer-level testing and minimizing damage of probes and interconnection structures.

Electromagnetic Interference Shielding from the Back-Side Metallization of the Chip in Fan-Out Wafer Level Package

Shielding against electromagnetic interference (EMI) is becoming increasingly important as electronics such as wearable devices, sensors, IoT, and smartphones become smaller, faster, and weigh less. Package level EMI shielding has several advantages over board level shielding, such as a higher packaging density and better design flexibility. We developed a new fan-out package structure using back-side under bump metallurgy (UBM) and a substrate (or metal carrier) to improve the thermal characteristics and reduce die shift. UBM and the substrate (or metal carrier), which consisted of highly conductive metals, is effective for EMI shielding. We study EMI shielding effects of UBM and the substrate (or metal carrier). To determine the EMI shielding of the UBM structures, Ti (17 nm thick) and Cu (70 nm thick) were sequentially deposited on a glass substrate using a direct-current (DC) magnetron sputtering system. Then Cu was electroplated or Ni-P was electroless plated with various thicknesses up to 10 µm. Samples were measured under 100 MHz and 1 GHz with 0 dB conditions using a spectra analyzer, which is a near-field measurement equipment. In unpatterened UBM, increase in the Cu or Ni thickness resulted in further enhanced EMI shielding. When the thickness of Cu UBM or Ni-P UBM was bigger than 5 µm or 3 µm, respectively, the UBM exhibited good EMI shielding. A double layer of Cu strips was formed on the back side of the chip to enhance EMI shielding. The larger the overlap between the Cu strip and the upper and lower layers, the better the EMI shielding effect. When this overlap was larger than 0.5 mm, the EMI SE was similar to that of a single unpatterned Cu layer. We demonstrated good EMI shielding in the double-layered structure with a large overlap width between the upper and lower Cu strips, and expect better moisture release in such structures.

Warpage Simulation During Fan-Out Wafer-Level Packaging Process with Uncertainty of Material Properties.

Along with the reduction in semiconductor chip size and enhanced performance of electronic devices, high input/output density is a desired factor in the electronics industry. To satisfy the high input/output density, fan-out wafer-level packaging has attracted significant attention. While fan-out wafer-level packaging has several advantages, such as lower thickness and better thermal resistance, warpage is one of the major challenges of the fan-out wafer-level packaging process to be minimized. There have been many studies investigating the effects of material properties and package design on warpage using finite element analysis. Current warpage simulations using finite element analysis have been routinely conducted with deterministic input parameters, although the parameter values are uncertain from the manufacturing point of view. This assumption may lead to a gap between the simulation and the field results. This paper presents an uncertainty analysis of wafer warpage in fan-out wafer-level packaging by using finite element analysis. Coefficient of thermal expansion of silicon is considered as a parameter with uncertainty. The warpage and the von Mises stress are calculated and compared with and without uncertainty.

Design of New Au–NiCo MEMS Vertical Probe for Fine-Pitch Wafer-Level Probing

As fine-pitch 3D wafer-level packaging becomes more popular in semiconductor industries, wafer-level prebond testing of various interconnect structures has become increasingly challenging. Additionally, improving the current-carrying capacity (CCC) and minimizing damage to the probe and micro-interconnect structures are very important issues in wafer-level testing. In this study, we propose an Au–NiCo MEMS vertical probe with an enhanced CCC to efficiently reduce the damage to the probe and various interconnect structures, including a solder ball, Cu pillar microbump, and TSV. The Au–NiCo probe has an Au layer inside the NiCo and an Au layer outside the surface of the NiCo probe to reduce resistivity and contact stress. The current-carrying capacity, contact stress, and deformation behavior of the probe and various interconnect structures were evaluated using numerical analyses. The Au–NiCo probe had a 150% higher CCC than the conventional NiCo probe. The maximum allowable current capacity of the 5000 µm-long Au–NiCo probe was 750 mA. The Au–NiCo probe exhibited less contact force and stress than the NiCo probe. The Au–NiCo probe also produced less deformation of various interconnect structures. These results indicate that the proposed Au–NiCo probe will be a prospective candidate for advanced wafer-level testing, with better probing efficiency and higher test yield and reliability than the conventional vertical probe.

Reliability and Performance of Wafer Level Fan Out Package for Automotive Radar

Embedded wafer level ball grid array (eWLB) or FO-WLP (Fan-out wafer-level packaging) is investigated as a package for MMICs (Monolithic Microwave Integrated Circuit) for automotive radar applications in the 77GHz range. Special focus is put on the thermo-mechanical performance to achieve automotive quality targets. The typical fatigue modes “solder ball fatigue” and “copper fatigue”, evolving during thermo-mechanical stress like cycling on board will be discussed. Simulation as well as experimental preparation results for typical fatigue levels are given. In addition, several influencing parameters are listed and rated regarding their effectiveness. The theoretical framework why solder ball fatigue is the only failure mode causing electrical failure is provided.
 
 The impact of different thermo-mechanically driven fatigue modes is discussed. The two important parameters to be considered for the functionality of the Radar system are RF (Radio Frequency) and thermal performance.
 
 For elaborating the RF performance with present fatigue modes, the phase shift between different channels and pads is analyzed by full-wave EM (Electromagnetic) simulation. It is found that for fatigue levels up to 90% the phase shift stays below specification for single fatigue modes and may approach specification only for an unlikely combination of all 90% fatigue modes.
 
 For assessing the thermal performance with present fatigue modes, thermal simulation as well as thermal measurements are used. Assuming 50% degradation in average for all thermal balls, an increase in RTH of up to about 30% is seen. On average for all thermal measurements, the deviation between measurement and simulation is within ±1°C.

Thermal Cycling Test and Simulation of Six-Side Molded Panel-Level Chip-Scale Packages (PLCSPs)

Abstract In this study, the reliability of the solder joints of a six-side molded panel-level chip-scale package (PLCSP) is investigated. Emphasis is placed on the thermal cycling test (−55°C Δ 125°C, 50-min cycle) of the six-side molded PLCSP on a printed circuit board. For comparison purpose, the one without six-side molded (ordinary) PLCSP is also subjected to the same test. The thermal cycling test results are plotted into a Weibull distribution, and the true Weibull slope and true characteristic life at 90% confidence are presented. The solder joint mean life ratio of these two cases and its confidence level are also determined. Furthermore, their solder joint failure location and failure mode are provided. Finally, a nonlinear, time- and temperature-dependent 3-D finite element simulation is performed for these two cases and correlated with the thermal cycling test results.

Semi-empirical law for fatigue resistance of redistribution layers in chip-scale packages

In this work we present a semi-empirical law for the fatigue resistance of redistribution layers (RDLs) in chip-scale packages. Fatigue of the copper RDL can lead to cracks in the RDL stack, which might eventually propagate into the die causing catastrophic electrical failure. In order to derive a semi-empirical law for RDL fatigue, the mechanical response of several test vehicles that showed this failure mode during temperature cycling tests have been simulated. The computed accumulated inelastic strain energy density in the RDL at the failed location shows a power-law dependence with the onset of fail found experimentally. The results show that the onset of fail does not scale with the package dimensions, as the RDL design itself plays a significant role. Furthermore, the design of the PCB is shown to have a dominant influence as well. To substantiate these experimental findings, micron-scale test coupons, consisting of representative copper traces on silicon wafers, were specially designed and fabricated in this study for investigation of the cyclic fatigue durability of RDL copper. The characteristic dimensions of the copper traces were selected to be comparable to those in RDLs. However, the fatigue resistance of these Cu-on-Si test coupons is significantly higher than that of RDL traces in actual applications. Therefore, we conclude that the semi-empirical law can be used for predictive modeling of the onset of RDL fail, only if a representative pool of test vehicles has been considered. More fundamental research is still needed to gain a complete understanding of the failure mechanism.

76- to 81-GHz CMOS Built-In Self-Test With 72-dB C/N and Less Than 1 ppm Frequency Tolerance for Multi-Channel Radar Applications

A built-in self-test (BIST) system with a 72-dB carrier-to-noise ratio (C/N) and less than 1-ppm frequency tolerance of down-converted BIST tone for a multi-channel radar application is presented. The BIST consists of a frequency doubler, an up-conversion mixer (UPMIX), a variable gain amplifier, a phase shifter, an eight-way splitter, and an RF PAD coupler for BIST signal distribution. The proposed BIST system can operate from 76 to 81 GHz, mixing with arbitrary offset frequencies from 600 kHz to 42.7 MHz generated by a fully-synchronized phase locked loop (PLL). The proposed UPMIX can generate zero or non-zero offset frequencies by switching between two modes flexibly implemented in the same layout area. The measured relative phase among all eight channels was less than 2° from −25 °C to 150 °C through on-chip 12-bit analog-to-digital converters (ADCs). The proposed BIST was fabricated using a 40-nm CMOS process and assembled with a wafer-level chip-sized package (WLCSP). Also, state-of-the-art BIST beamformer analyses were demonstrated as one of the future methods for self-diagnosis with a null-depth monitoring for a multi-channel radar application.

Evaluation of the Quality of BGA Solder Balls in FCBGA Packages Subjected to Thermal Cycling Reliability Test Using Laser Ultrasonic Inspection Technique

In modern integrated circuit (IC) packaging, it is difficult to perceive and evaluate the quality of the solder ball interconnections due to their complex hidden physical configuration and miniaturization. Laser ultrasonic inspection (LUI) technique is a novel, nondestructive, and noncontact method that has achieved great success in evaluating the quality of interconnections in chip-scale and ball-grid array (BGA) packages. In this article, an enhanced dual-fiber array LUI system is used to evaluate the quality of BGA solder balls in advanced industrial flip-chip BGA packages subjected to thermal cycling reliability tests. LUI results are validated with electrical testing, scanning electron microscope (SEM), and dye-and-pry results. LUI results are well correlated with the intermetallic compound cracks in BGA solder balls observed using SEM, and dye-and-pry. This study demonstrates the feasibility of using the LUI system for one of the modern IC packages and the potential to use the LUI system for future advanced IC packages such as 3-D packaging.

Reliability Evaluation of Fan-Out Type 3D Packaging-On-Packaging.

The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. To reduce the package footprint and improve system performance, many applications have adopted packaging-on-packaging (PoP) architecture. Given its inherent characteristics, glass is a good material for high-speed transmission applications. Therefore, this study proposes a fan-out wafer-level packaging (FO-WLP) with glass substrate-type PoP. The reliability life of the proposed FO-WLP was evaluated under thermal cycling conditions through finite element simulations and empirical calculations. Considering the simulation processing time and consistency with the experimentally obtained mean time to failure (MTTF) of the packaging, both two- and three-dimensional finite element models were developed with appropriate mechanical theories, and were verified to have similar MTTFs. Next, the FO-WLP structure was optimized by simulating various design parameters. The coefficient of thermal expansion of the glass substrate exerted the strongest effect on the reliability life under thermal cycling loading. In addition, the upper and lower pad thicknesses and the buffer layer thickness significantly affected the reliability life of both the FO-WLP and the FO-WLP-type PoP.

Wafer Level Packaging Technology Applied to Pixel Detectors

Pixel technology is commonly used in the tracking systems of High Energy Physics detectors with physical areas that have largely increased in the last decades. To ease the production of several square meters of sensitive area, the possibility of using the industrial Wafer Level Packaging to reassemble good single sensor tiles from multiple wafers into a reconstructed full wafer is investigated. This process reconstructs wafers by compression molding using silicon charged epoxy resin. We tested high glass transition temperature low-stress epoxy resins filled with silica particles to best match the thermal expansion of the silicon die. These resins are developed and characterized for industrial processes, designed specifically for fan-out wafer-level package and panel-level packaging. In order to be compatible with wafer processing during the hybridization of the pixel detectors, such as the bump-bonding, the reconstructed wafer must respect challenging technical requirements. Wafer planarity, tile positioning accuracy, and overall thickness are amongst the main ones. In this paper the description of the process is given and preliminary results on a few reconstructed wafers using dummy tiles are reported. Strategies for Wafer Level Packaging improvements are discussed together with future applications to 3D sensors or CMOS pixel detectors.

Laue microdiffraction evaluation of bending stress in Au wiring formed on chip-embedded flexible hybrid electronics

Au redistribution layers 10 to 100 μm wide were fabricated on heterogeneously integrated advanced flexible hybrid electronics (FHE) substrates formed by a die-first approach based on fan-out wafer-level packaging. The formed Au metal wiring was meticulously studied for locally induced mechanical stress upon bending (bending radius, BR 20 mm) using Laue microdiffraction (LμD) with synchrotron radiation. It was inferred from the LμD data that upon bending the FHE substrate up to the BR of 20 mm, the Au metal wiring (10 mm long, 100 μm wide, and 500 nm thick) experienced mechanical bending stress amounting to 250 ∼ 300 MPa. The stress values obtained from the LμD studies were close to the stress value of 350 MPa obtained by simulation.

Low temperature curing polyimides with covalent-boned 5-aminobenzimidazole

Polyimides (PIs) with remarkable mechanical, thermal, dielectric properties have been extensively employed in electronic package of integrated circuit industry. However, PI is imidized at high temperature (>350 °C) traditionally, which limits its application in thin-film transistor and fan-out wafer level package (FOWLP). In this work, active curing catalyst of 5-aminobenzimidazole is introduced in covalent bond to get a low temperature curable polyimide with superior comprehensive properties. The results prove that PI-3 can be imidized completely at 200 °C in 2 h and the imidization index could be as high as 1.03. Besides, the PI films exhibit excellent thermal stability of which the temperature for 5% weight loss is as high as 526 °C and glass transition temperature is 428 °C which is obtained by dynamic mechanical analyzer. Moreover, the tensile test shows the tensile strength of PI-3 is 91 MPa and elongation at break is about 15%. All these results prove the superior performance of the low temperature curing PIs, showing great potentials in the advanced package in the FOWLP and the others.

Solder Joint Reliability Assessment and Pad Size Studies of FO-WLP With Glass Substrate

In recent years, the use of fan-out packaging solutions has boomed in semiconductor-related fields. There are primarily two versions used for mass production: wafer level and panel level. In this research, a glass substrate was used in the design of a fan-out wafer-level package (FO-WLP) and simulations were conducted to predict the reliability of the solder joints. The advantages of glass substrates are their excellent electrical properties, good mechanical rigidity, flatness, and adjustable coefficient of thermal expansion. To verify the robustness of the simulations, a FO-WLP test vehicle was designed, manufactured, and tested under JEDEC thermal cycling condition. In this study, the simulation results were used in an empirical equation to estimate the reliability of the FO-WLP under accelerated thermal-cycling conditions. After simulation validated by experiments, parametric simulations of different design factors can be performed. Using this methodology, we developed a reliable finite element analysis procedure. Thus, structural optimization of the FO-WLP was possible via simulations using various design factors to improve its reliability. The simulation results indicate that a suitable combination of upper, lower pad sizes and the thickness of buffer layer could significantly enhance the reliability life of FO-WLP, and that designers should devote greater attention to these factors to achieve better long-term reliability performance.

Solder joint reliability based on creep strain energy density for SAC305 and doped SAC solders

Parallel to the development of new lead-free solders, electronic packaging has gone through a considerable evolution. A redistribution of layers allows the increase of functionality by increasing the number of inputs/outputsin the packagewhile reducing the size. The reliability of the package is strongly influenced by the reliability of the interconnects. During production and service life, there are thermal processes involved that may lead to thermal fatigue. In this work, a two-dimensional finite elementmodel of a Fan-Out Wafer Level Packaging (FO-WLP) was built, and simulations of thermal test cycles were carried out varying the solder interconnect material: SAC305, SACQ, SACR, orInnoLot. A thermal oscillating load from –40°C to 125°C was applied to the packaging for three hours.State of the art concerning solder joint reliability models based on creep behavior reveals the benefit of using energy-based parameters, as cycles to failure are inversely proportional to the average creep strain energy density.Based on theaverage creep strain energy density simulation results, the reliability of the package withdifferent solderswas compared.The qualitative results suggestthat SACQ has a significant advantage in the operational lifetime compared toSACR, InnoLot, and SAC305.

5-in-1 Fan-Out Wafer-Level Packaging Technology with One AI Chip and Four Memory Chips for Internet of Things Modules

5-in-1 Fan-Out Wafer-Level Packaging Technology with One AI Chip and Four Memory Chips for Internet of Things Modules