Electromagnetic Interference Shielding from the Back-Side Metallization of the Chip in Fan-Out Wafer Level Package

Abstract

Shielding against electromagnetic interference (EMI) is becoming increasingly important as electronics such as wearable devices, sensors, IoT, and smartphones become smaller, faster, and weigh less. Package level EMI shielding has several advantages over board level shielding, such as a higher packaging density and better design flexibility. We developed a new fan-out package structure using back-side under bump metallurgy (UBM) and a substrate (or metal carrier) to improve the thermal characteristics and reduce die shift. UBM and the substrate (or metal carrier), which consisted of highly conductive metals, is effective for EMI shielding. We study EMI shielding effects of UBM and the substrate (or metal carrier). To determine the EMI shielding of the UBM structures, Ti (17 nm thick) and Cu (70 nm thick) were sequentially deposited on a glass substrate using a direct-current (DC) magnetron sputtering system. Then Cu was electroplated or Ni-P was electroless plated with various thicknesses up to 10 µm. Samples were measured under 100 MHz and 1 GHz with 0 dB conditions using a spectra analyzer, which is a near-field measurement equipment. In unpatterened UBM, increase in the Cu or Ni thickness resulted in further enhanced EMI shielding. When the thickness of Cu UBM or Ni-P UBM was bigger than 5 µm or 3 µm, respectively, the UBM exhibited good EMI shielding. A double layer of Cu strips was formed on the back side of the chip to enhance EMI shielding. The larger the overlap between the Cu strip and the upper and lower layers, the better the EMI shielding effect. When this overlap was larger than 0.5 mm, the EMI SE was similar to that of a single unpatterned Cu layer. We demonstrated good EMI shielding in the double-layered structure with a large overlap width between the upper and lower Cu strips, and expect better moisture release in such structures.