Abstract
The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. To reduce the package footprint and improve system performance, many applications have adopted packaging-on-packaging (PoP) architecture. Given its inherent characteristics, glass is a good material for high-speed transmission applications. Therefore, this study proposes a fan-out wafer-level packaging (FO-WLP) with glass substrate-type PoP. The reliability life of the proposed FO-WLP was evaluated under thermal cycling conditions through finite element simulations and empirical calculations. Considering the simulation processing time and consistency with the experimentally obtained mean time to failure (MTTF) of the packaging, both two- and three-dimensional finite element models were developed with appropriate mechanical theories, and were verified to have similar MTTFs. Next, the FO-WLP structure was optimized by simulating various design parameters. The coefficient of thermal expansion of the glass substrate exerted the strongest effect on the reliability life under thermal cycling loading. In addition, the upper and lower pad thicknesses and the buffer layer thickness significantly affected the reliability life of both the FO-WLP and the FO-WLP-type PoP.
Highlights
The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research
We proposed an fan-out wafer-level packaging (FO-WLP) with a glass substrate architecture and used it as a PoP
After onboard thermal cycling testing (OBTCT), we inspected the failed test vehicle and found that the crack was located atop the solder joint with the largest distance from the neutral point (DNP)
Summary
The development of fan-out packaging technology for fine-pitch and high-pin-count applications is a hot topic in semiconductor research. 3D integrated systems are becoming increasingly important in the realization of lightweight devices with higher performance and better miniaturization. These systems effectively reduce the package footprint and weight, and improve system performance by reducing the system circuit communication length. Packaging-on-packaging (PoP) technology allows packages to be stacked three-dimensionally, achieving highdensity integration and improving chip-to-chip performance (e.g., in applications with high-frequency data exchange between application processes and memory) [1,2,3]. The coefficient of thermal expansion (CTE) of glass can be optimized to reduce warpage [4,5] and improve the reliability life of stacked fan-out wafer-level packaging (FO-WLP). Before mass production, packaging must pass reliability life testing under thermal cycling loading; in the JEDEC(Joint Electron Device Engineering
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