Wafer Level Packaging Research Articles

Optimization of TSV Leakage in Via-Middle TSV Process for Wafer-Level Packaging

Through silicon via (TSV) offers a promising solution for the vertical connection of chip I/O, which enables smaller and thinner package sizes and cost-effective products by using wafer-level packaging instead of a chip-level process. However, TSV leakage has become a critical concern in the BEOL process. In this paper, a Cu-fulfilled via-middle TSV with 100 µm depth embedded in 0.18 µm CMOS process for sensor application is presented, focusing on the analysis and optimization of TSV leakage. By using etch process, substrate defect, and thermal processing co-optimization, TSV leakage failure can be successfully avoided, which can be very instructive for the improvement in TSV wafer-level package yield as well as device performance in advanced semiconductor technology.

A physical lifetime prediction methodology for IGBT module by explicit emulation of solder layer degradation

Physical lifetime prediction methods based on inelastic strain energy density (energy-based lifetime prediction) have been proven to be effective in producing reliable results on small solder joints (ball-grid arrays or chip-scale package) due to their capabilities to represent physical characteristics of soldering materials and loading history. However, in the existing energy-based lifetime models for solder layer failure the inelastic strain energy density is usually assumed to unchanged during aging, which is untrue particularly for large-area solder joints when crack propagation is considered. In this paper, an energy-based lifetime prediction method is proposed for failure of IGBT modules by explicit emulation of solder layer degradation. Inelastic strain energy density variances with respect to aging are meticulously modeled. The large-area solder layer is evenly divided into meshed elements, birth and death technique in finite element analysis (FEA) is used to successively emulate crack propagation. In this way, the increment of thermal resistance due to the solder layer degradation can be predicted. The lifetime prediction results by our proposed method show nice agreement with the experiment under different aging conditions.

A Novel High-Q Dual-Mass MEMS Tuning Fork Gyroscope Based on 3D Wafer-Level Packaging.

Tuning fork gyroscopes (TFGs) are promising for potential high-precision applications. This work proposes and experimentally demonstrates a novel high-Q dual-mass tuning fork microelectromechanical system (MEMS) gyroscope utilizing three-dimensional (3D) packaging techniques. Except for two symmetrically decoupled proof masses (PM) with synchronization structures, a symmetrically decoupled lever structure is designed to force the antiparallel, antiphase drive mode motion and eliminate low frequency spurious modes. Thermoelastic damping (TED) and anchor loss are greatly reduced by the linearly coupled, momentum- and torque-balanced antiphase sense mode. Moreover, a novel 3D packaging technique is used to realize high Q-factors. A composite substrate encapsulation cap, fabricated by through-silicon-via (TSV) and glass-in-silicon (GIS) reflow processes, is anodically bonded to the wafer-scale sensing structures. A self-developed control circuit is adopted to realize loop control and characterize gyroscope performances. It is shown that a high-reliability electrical connection, together with a high air impermeability package, can be fulfilled with this 3D packaging technique. Furthermore, the Q-factors of the drive and sense modes reach up to 51,947 and 49,249, respectively. This TFG realizes a wide measurement range of ±1800 °/s and a high resolution of 0.1°/s with a scale factor nonlinearity of 720 ppm after automatic mode matching. In addition, long-term zero-rate output (ZRO) drift can be effectively suppressed by temperature compensation, inducing a small angle random walk (ARW) of 0.923°/√h and a low bias instability (BI) of 9.270°/h.

An Overview of AI-Assisted Design-on-Simulation Technology for Reliability Life Prediction of Advanced Packaging.

Several design parameters affect the reliability of wafer-level type advanced packaging, such as upper and lower pad sizes, solder volume, buffer layer thickness, and chip thickness, etc. Conventionally, the accelerated thermal cycling test (ATCT) is used to evaluate the reliability life of electronic packaging; however, optimizing the design parameters through ATCT is time-consuming and expensive, reducing the number of experiments becomes a critical issue. In recent years, many researchers have adopted the finite-element-based design-on-simulation (DoS) technology for the reliability assessment of electronic packaging. DoS technology can effectively shorten the design cycle, reduce costs, and effectively optimize the packaging structure. However, the simulation analysis results are highly dependent on the individual researcher and are usually inconsistent between them. Artificial intelligence (AI) can help researchers avoid the shortcomings of the human factor. This study demonstrates AI-assisted DoS technology by combining artificial intelligence and simulation technologies to predict wafer level package (WLP) reliability. In order to ensure reliability prediction accuracy, the simulation procedure was validated by several experiments prior to creating a large AI training database. This research studies several machine learning models, including artificial neural network (ANN), recurrent neural network (RNN), support vector regression (SVR), kernel ridge regression (KRR), K-nearest neighbor (KNN), and random forest (RF). These models are evaluated in this study based on prediction accuracy and CPU time consumption.

A Hybrid Antenna in Package Solution Using FOWLP Technology

Abstract Widespread millimeter wave applications have promoted rapid development of system in package (SiP) and antenna in package (AiP). Most AiP structures take the form of flip chip onto antenna substrate, where signal interconnect losses are introduced by solder bumps. The integration may be unavailable for chips with fine pad pitches. Fan-out wafer level package (FOWLP) with antenna patterning on redistributed layers (RDL) is another method for millimeter wave AiP. In this project, a hybrid integration AiP structure is developed. The microwave monolithic integrated circuit (MMIC) chip and antenna unit are integrated with chip-first FOWLP process. Multilayer organic substrate with fine pitch RDL interconnections meets the requirements of wideband antenna design. Modified coplanar waveguide is adopted to feed 2 × 2 aperture array formed on RDL layer. Package warpage is measured using Shadow Moire techniques. The antenna forms an aperture-coupled stacked patch array with bandwidth 25% and gain 8.5dBi for 60 GHz digital communication system. The proposed approach is a convenient hybrid integration solution adopting FOWLP process for millimeter wave AiP systems.

Robust Pressure Sensor in SOI Technology with Butterfly Wiring for Airfoil Integration.

Current research in the field of aviation considers actively controlled high-lift structures for future civil airplanes. Therefore, pressure data must be acquired from the airfoil surface without influencing the flow due to sensor application. For experiments in the wind and water tunnel, as well as for the actual application, the requirements for the quality of the airfoil surface are demanding. Consequently, a new class of sensors is required, which can be flush-integrated into the airfoil surface, may be used under wet conditions—even under water—and should withstand the harsh environment of a high-lift scenario. A new miniature silicon on insulator (SOI)-based MEMS pressure sensor, which allows integration into airfoils in a flip-chip configuration, is presented. An internal, highly doped silicon wiring with “butterfly” geometry combined with through glass via (TGV) technology enables a watertight and application-suitable chip-scale-package (CSP). The chips were produced by reliable batch microfabrication including femtosecond laser processes at the wafer-level. Sensor characterization demonstrates a high resolution of 38 mVV−1 bar−1. The stepless ultra-smooth and electrically passivated sensor surface can be coated with thin surface protection layers to further enhance robustness against harsh environments. Accordingly, protective coatings of amorphous hydrogenated silicon nitride (a-SiN:H) and amorphous hydrogenated silicon carbide (a-SiC:H) were investigated in experiments simulating environments with high-velocity impacting particles. Topographic damage quantification demonstrates the superior robustness of a-SiC:H coatings and validates their applicability to future sensors.

Investigation of the microstructural evolution and detachment of Co in contact with Cu–Sn electroplated silicon chips during solid-liquid interdiffusion bonding

Solid-liquid interdiffusion (SLID) bonding is one of the most promising novel methods for micro-(opto)-electromechanical system (MEMS/MOEMS) wafer-level packaging. However, the current SLID bonding solutions require the use of an electrochemical deposition method for MEMS/MOEMS wafers as well, which significantly complicates the process integration options. Hence, this work proposes Co as a potential option for compatible contact metallization on MEMS/MOEMS wafers to utilize mature Cu–Sn SLID bonding. The focus of this study is on gaining a fundamental understanding of the microstructural formation and evolution of Co substrates in contact with Cu–Sn electroplated silicon wafers and identifying possible failures of joints during bonding, which are prerequisites for guaranteeing devices’ manufacturability, functionality, and long-term reliability. The effect of bonding time and temperature on the microstructural evolution and phase formation of Co substrates in contact with Cu–Sn electroplated silicon chips was investigated. Moreover, a phase diagram of the Co–Cu–Sn ternary system was thermodynamically evaluated based on experimental data. Samples were successfully bonded at 250 °C for 1500 and 2000 s and at 280 °C for 1000 s. The main interfacial intermetallic compounds were identified as (Cu,Co)6Sn5, Cu3Sn, and (Co,Cu)Sn3. Co stabilized the high-temperature hexagonal (η) Cu6Sn5 phase down to room temperature. Bond detachment was observed when applying either a higher bonding temperature or a longer bonding time. Two critical factors that cause detachment during bonding were recognized: first, a change in thermodynamic equilibrium when exceeding the maximum allowed Co content in Cu6Sn5 formed adjacent to the CoSn3 phase and a discontinuous change in the Co content in the Cu6Sn5 grown on the Cu and Co sides; second, stress exerted due to the rapid growth of (Co,Cu)Sn3 between the Co substrate and (Cu,Co)6Sn5. Therefore, achieving successful bonding in the Co–Sn–Cu SLID system requires governing the amount of dissolved Co atoms in liquid Sn and the CoSn3 formation, both of which can be achieved by manipulating the relative thickness of the Co, Cu, and Sn layers. The observations and calculations in this work show that a prerequisite for obtaining successful bonding in the Co–Sn–Cu SLID system at 250 °C is a Co–to–Sn thickness ratio of 0.04 or less.

Reliable and Efficient Phosphor-in-Glass-Based Chip-Scale Packaging for High-Power White LEDs

A white light-emitting diode (WLED) with chip-scale packaging (CSP) has wide applications due to its high power density, small size, and high process integration. The phosphor converter of the CSP WLED needs to endure huge heat shock from LED chips and phosphor conversion. In this work, we proposed a phosphor-in-glass (PiG)-based CSP for high-power WLEDs. A wafer PiG was prepared by printing and sintering a phosphor glass film on a glass plate and then cut into a chip-scale PiG for the fabrication of PiG-CSP WLEDs. The optical performances of PiG-CSP WLEDs were optimized by adjusting the film thickness of PiG. Consequently, the PiG-CSP WLED emits a cool white light with optimal light performances at a film thickness of 88 μm. The related luminous efficiency (LE), correlated color temperature (CCT), and chromaticity coordinate are 108.8 lm/W, 5796 K, and (0.3256 and 0.3467), respectively. The down-PiG-CSP structure achieves higher LE and lower CCT than the up-PiG-CSP structure. Compared with the traditional phosphor-in-silicone (PiS)-CSP WLED, the PiG-CSP WLED avoids the carbonization of the converter and displays excellent thermal stability under high input current. The results determine that the PiG-CSP is a reliable and efficient packaging technology for high-power WLEDs.

Development of Computer Intelligent System-Level Electronic Integrated Package Microsystem Technology

Electronic product systems are gradually developing in the direction of miniaturization and high integration, and the post-Moore era has arrived. The boundaries between integrated circuit chips and integrated packaging components are becoming blurred, and a new situation of integration and development has been formed for various system-level applications. Microsystems bring together innovations and breakthroughs in multiple disciplines and technologies, and have been widely used in both military and civilian fields. This article provides an overview of the current status and future development trends of advanced packaging technologies in the field of integrated circuits, focusing on existing advanced packaging technologies, such as wafer-level packaging, 2.5D, 3D, SIP and Chiplet integration, and other advanced packaging technologies. And introduced the application of microsystem technology in the microelectronics industry, military field and other civilian fields. At the end of the article, the microsystem technology is prospected.

Developing Cost-Effective Ultrathin Reliable High Power White LED Emitters

A packaging approach for cost-effective and ultrathin high-power phosphor-based white light-emitting-diode (WLED) emitters with outstanding reliability is presented. By removing the encapsulant in the conventional method, the new approach employs a single silicone-phosphor thin layer instead of multiple phosphor layers in chip-scale package (CSP) WLED for both encapsulations, as well as wavelength conversion. It is demonstrated that the presented WLEDs exhibit superior optical and thermal performance and lifetime durability. Accordingly, the present work offers a high reliability, cost-effective alternative approach for ultrathin high power WLED emitters with significant advantages over the conventional packaging structure and chip-scale packaging methods.

The Redistribution Layer-First Embedded Fan-Out Wafer Level Packaging for 2-D Ultrasonic Transducer Arrays

In this letter, the redistribution layer-first embedded fan-out wafer-level packaging (RDL-first FO-WLP) for 2-D ultrasonic transducer arrays with individual electrical connection is proposed. This process provides the capability of manufacturing thin film circuit with multilayer RDLs and allows signals of elements in arrays being fanned-out to a region larger than the array size. An anisotropic conductive film (ACF) with low curing temperature is employed to provide the electrical and mechanical connection between RDLs and ultrasonic transducer arrays. The thin film circuit with multilayer RDLs and ultrasonic transducer arrays were respectively fabricated and the curing temperature of ACF is close to half of the Curie temperature of the array. This process avoids ultrasonic transducer arrays losing their piezoelectric property, for ultrasonic transducer arrays are not suffering from the high curing temperature of the passivation layers and of the bonding process.

Test Temperature Calibration Using Inertial MEMS Voltage-Temperature Characteristics for ATE Setup

In the chip-scale package final test, temperature is one of the main components as this is also indicated on once specification on electrical parameters that are temperature sensitive especially for inertial Micro-Electro- Mechanical Systems (MEMS) accelerometers. The voltagetemperature relationship of an accelerometer has been presented and used to calibrate test temperature on Automated Test Equipment (ATE) setup. Bench reference data of a set of units were gathered to correlate with the Device under Test (DUT) temperature with the raw ATE handler test temperature using linear regression. Offset test temperature or the temperature error was calculated across all sites to adjust the new ATE handler test temperature. After which, the correlation between the bench reference data and the gathered ATE data of the 20 golden units from two test flows with 2.3 seconds and 200 milliseconds respectively both with 4-site enabled testing was validated that all DUT temperature is within acceptable temperature window of +/- 3°C, also less standard deviation for longer test time by only 0.0011 and all 20 golden units passed for both test flows. Lastly, the comparison of the newly calibrated test handler using the voltage-temperature relationship which had 0.0011, 0.0011, and 0.0012 SD of data, and the static calibrated test handlers which had 0.0057, 0.0078, and 0.010 SD of data for each lot 1, 2, and 3 respectively show up to 8x improvement in SD of the DUT temperature in ATE.

Flip Chip - Chip Scale Package Bonding Technology with Type 7 Solder Paste Printing

In this study, thermo-compression(TC) and vacuum reflow(VR) bonding processes of fine pitch interconnection were optimized using Type 7 Sn-3.0Ag-0.5Cu solder paste. A chip with Cu pillar Sn-2.5Ag bumps and BT substrate with ENEPIG surface finish were used, and the thickness and the aperture ratio of the metal mask were 30 ㎛/50 ㎛ and 70%/100%, respectively. As a result of optimizing the printing process, a metal mask with a thickness of 30 ㎛ and an aperture ratio of 100% was selected. As a result of the TC and VR bonding processes optimization, Cu6Sn5 and (Cu,Ni)6Sn5 IMC layers were formed on the top and bottom of the solder joint, respectively. In the conventional TC process sample, the thickness of the solder was measured to be 4.1 ㎛, and the IMC thickness ratio was calculated to be 40%. Also, in the TC and VR process samples with solder paste, the thickness of the solder was measured to be 6.5 ㎛ and 10.3 ㎛, respectively, and the ratio of the IMC thickness was calculated to be about 32% and 43%. It was expected that it would be beneficial to reliability by reducing the occurrence and propagation of cracks in the solder joint due to the effect of lowering the IMC thickness ratio as the volume of the solder becomes larger than that of the conventional TC process.

Solder Joint Reliability Risk Estimation by AI-Assisted Simulation Framework with Genetic Algorithm to Optimize the Initial Parameters for AI Models

Solder joint fatigue is one of the critical failure modes in ball-grid array packaging. Because the reliability test is time-consuming and geometrical/material nonlinearities are required for the physics-driven model, the AI-assisted simulation framework is developed to establish the risk estimation capability against the design and process parameters. Due to the time-dependent and nonlinear characteristics of the solder joint fatigue failure, this research follows the AI-assisted simulation framework and builds the non-sequential artificial neural network (ANN) and sequential recurrent neural network (RNN) architectures. Both are investigated to understand their capability of abstracting the time-dependent solder joint fatigue knowledge from the dataset. Moreover, this research applies the genetic algorithm (GA) optimization to decrease the influence of the initial guessings, including the weightings and bias of the neural network architectures. In this research, two GA optimizers are developed, including the “back-to-original” and “progressing” ones. Moreover, we apply the principal component analysis (PCA) to the GA optimization results to obtain the PCA gene. The prediction error of all neural network models is within 0.15% under GA optimized PCA gene. There is no clear statistical evidence that RNN is better than ANN in the wafer level chip-scaled packaging (WLCSP) solder joint reliability risk estimation when the GA optimizer is applied to minimize the impact of the initial AI model. Hence, a stable optimization with a broad design domain can be realized by an ANN model with a faster training speed than RNN, even though solder fatigue is a time-dependent mechanical behavior.

Design and Implementation of RF Front-End Module Based on 3D Heterogenous-Integrated Wafer-Level Packaging

In this paper, a three-dimensional heterogenous-integrated (3DHI) wafer-level packaging (WLP) process is proposed, and a radio frequency (RF) front-end module with two independent ultra-high frequency (UHF) receiving channels are designed and implemented, which covers 400 MHz–600 MHz and 2050 MHz–2200 MHz respectively for unmanned aerial vehicle (UAV) applications. The module is formed by wafer-to-wafer (W2W) bonding of two high-resistivity silicon (HR-Si) interposers with embedded bare dies and through silicon via (TSV) interconnections. Double-sided deep reactive ion etching (DRIE) and conformal electroplating process are introduced to realize the high-aspect-ratio TSV connection within 290 µm-thick cap interposer. Co-plane waveguide (CPW) transmission lines are fabricated as the process control monitor (PCM), the measured insertion loss of which is less than 0.18 dB/mm at 35 GHz. The designed RF front-end module is fabricated and measured. The measured return loss and gain of each RF channel is better than 13 dB and 21 dB, and the noise figure is less than 1.5 dB. In order to evaluate the capability of the 3DHI process for multi-layer interposers, the module is re-designed and fabricated with four stacked high-resistivity silicon interposers. After W2W bonding of two pairs of interposers and wafer slicing, chip-to chip (C2C) bonding is applied to form a four-layer module with operable temperature gradient.

Correlation Studies Between Laser Ultrasonic Inspection Data and Finite-Element Modeling Results in Evaluation of Solder Joint Quality in Microelectronic Packages

Abstract Laser ultrasonic inspection (LUI) is a nondestructive and noncontact technique to evaluate the quality of solder ball interconnections in area-array micro-electronic packages. Dual-Fiber Array Laser Ultrasonic Inspection System was demonstrated identifying defects and failures in chip-scale packages, ball grid array packages, and flip-chip ball grid array packages. The location and severity of the defects and failures in packages have been identified accurately using this system. Further, it is important to establish the correlation between LUI results and the severity of the failures for failure mode analysis, which will enable us to eliminate the need for destructive testing and allow the study of failure evolution in a given sample under continued reliability testing. This paper discusses correlation studies between experimental LUI results and finite-element simulation results from the flip-chip ball grid array packages subjected to thermal cycling reliability testing. The correlation equations will help in predicting the severity of the failures at a given number of thermal cycles based on LUI results. Furthermore, the life of the micro-electronic packages can be predicted accurately from LUI results at a fewer number of thermal cycles.

Ultra-Low Stress Die Attachment Based on a Stacked Multilayer Substrate

This letter reports a novel approach for ultra-low stress die attachment for microelectromechanical system (MEMS) devices based on a stacked multilayer substrate. The substrate consists of stacked layers of alternating low and high coefficient of thermal expansion (CTE) materials. The effective CTE of the substrate is determined by adjusting the thickness ratio of the stacked layers, hence, the CTE mismatch between the substrate and the MEMS devices can be tuned to minimize the packaging stress during die attachment. Simplified block structures are fabricated to verify the effectiveness of the reported approach. The measurement results agree well with the theoretical analysis, and the finite-element method (FEM) simulation. The maximum deflection of a packaged 3×5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die is reduced to be lower than 10 nm using a quartz glass-alumina stacked layer substrate, which is approximately 30 times lower than that using a conventional alumina substrate. Moreover, the thermal behavior of the packaging chips utilizing this approach is measured in a temperature range of 25 °C to 150 °C. This work highlights an effective and simple way for the chip-scale package of MEMS devices with strict requirements for low packaging stress. [2021-0043]

Development and Reliability Study of 3-D Wafer Level Packaging for SAW Filter Using Thin Film Capping

The rapid growth of the advanced consumer 5G wireless mobile phones has propelled the demands of fabricating surface acoustic wave (SAW) filters with smaller size and high performance. Three-dimension wafer-level package (3-D WLP) for SAW filter is a promising solution to replace conventional surface mounted technology and chip-scale packaging. In this article, a new WLP for SAW filter with a size of 1.3 mm ×1.1 mm ×0.35 mm is developed using thin dry film capping. The new 3-D WLP significantly reduces the overall thickness which is particularly meaningful for low-profile smartphones and tablets. A number of key processes were developed. To improve the quality, finite element modeling (FEM) is used to simulate the mechanical stress to optimize cavity structure. Reliability tests were performed and the results indicated that there were no significant frequency response changes occurred and low insertion loss (IL) in pass band was less than 0.2 dB after pro-conditional level 3 test, unbiased highly accelerated stress (uHAST) test, and temperature cycling (TC) test on SAW filter packages. It can be concluded that 3-D WLP for SAW filter achieves miniaturization, good electrical performance, and reliability.

Development of three-dimensional wafer level chip scale packaging using via last TSV and UV laser releasable temporary bonding technologies

Development of three-dimensional wafer level chip scale packaging using via last TSV and UV laser releasable temporary bonding technologies

Packaging of semiconductor thermoelectric energy generators with in-plane thermocouples and isolation cavities

With the advent of semiconductor foundry services, thermoelectric energy generator (TEG) by CMOS/BiCMOS process has been preferable for production yield, cost effectiveness, and device scalability. The thermocouples in semiconductor TEG often have thermal isolation cavity to reduce heat loss. Both die- and wafer-packaging are proposed in this work to seal the cavity, prevent moisture/dirt from contamination, and avoid short circuit condition in the thermocouples for TEG applications in wearable devices. For a TEG design by 3P6M (3 polysilicon layers and 6 metal layers) BiCMOS process, the die-level packaging by aluminum film of thickness 50 μm over the TEG is shown to be effective, though there is about 23 % temperature gradient loss by the packaging. The voltage factor is 18.22 V/cm2K, about 77 % of that before packaging. For a TEG design by 1P6M CMOS process, the wafer-level packaging by bonding two identical TEG device wafers is shown to have about 22 % loss in temperature gradient. Yet the TEG performance is increased significantly on the same footprint because of doubling area density, and hence doubling both the power factor and voltage factor. The power factor and voltage factor is 0.164 μW/cm2 K2 and 24.32 V/cm2K, respectively, on the TEG in series circuit after packaging.