Ultra-Low Stress Die Attachment Based on a Stacked Multilayer Substrate

Abstract

This letter reports a novel approach for ultra-low stress die attachment for microelectromechanical system (MEMS) devices based on a stacked multilayer substrate. The substrate consists of stacked layers of alternating low and high coefficient of thermal expansion (CTE) materials. The effective CTE of the substrate is determined by adjusting the thickness ratio of the stacked layers, hence, the CTE mismatch between the substrate and the MEMS devices can be tuned to minimize the packaging stress during die attachment. Simplified block structures are fabricated to verify the effectiveness of the reported approach. The measurement results agree well with the theoretical analysis, and the finite-element method (FEM) simulation. The maximum deflection of a packaged 3×5 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> die is reduced to be lower than 10 nm using a quartz glass-alumina stacked layer substrate, which is approximately 30 times lower than that using a conventional alumina substrate. Moreover, the thermal behavior of the packaging chips utilizing this approach is measured in a temperature range of 25 °C to 150 °C. This work highlights an effective and simple way for the chip-scale package of MEMS devices with strict requirements for low packaging stress. [2021-0043]