Packaging of semiconductor thermoelectric energy generators with in-plane thermocouples and isolation cavities

Abstract

With the advent of semiconductor foundry services, thermoelectric energy generator (TEG) by CMOS/BiCMOS process has been preferable for production yield, cost effectiveness, and device scalability. The thermocouples in semiconductor TEG often have thermal isolation cavity to reduce heat loss. Both die- and wafer-packaging are proposed in this work to seal the cavity, prevent moisture/dirt from contamination, and avoid short circuit condition in the thermocouples for TEG applications in wearable devices. For a TEG design by 3P6M (3 polysilicon layers and 6 metal layers) BiCMOS process, the die-level packaging by aluminum film of thickness 50 μm over the TEG is shown to be effective, though there is about 23 % temperature gradient loss by the packaging. The voltage factor is 18.22 V/cm2K, about 77 % of that before packaging. For a TEG design by 1P6M CMOS process, the wafer-level packaging by bonding two identical TEG device wafers is shown to have about 22 % loss in temperature gradient. Yet the TEG performance is increased significantly on the same footprint because of doubling area density, and hence doubling both the power factor and voltage factor. The power factor and voltage factor is 0.164 μW/cm2 K2 and 24.32 V/cm2K, respectively, on the TEG in series circuit after packaging.