Abstract
Through silicon via (TSV) offers a promising solution for the vertical connection of chip I/O, which enables smaller and thinner package sizes and cost-effective products by using wafer-level packaging instead of a chip-level process. However, TSV leakage has become a critical concern in the BEOL process. In this paper, a Cu-fulfilled via-middle TSV with 100 µm depth embedded in 0.18 µm CMOS process for sensor application is presented, focusing on the analysis and optimization of TSV leakage. By using etch process, substrate defect, and thermal processing co-optimization, TSV leakage failure can be successfully avoided, which can be very instructive for the improvement in TSV wafer-level package yield as well as device performance in advanced semiconductor technology.
Highlights
Smart mobile terminals have continuously driven the scaling of packaging density, especially in the vertical dimension with lowered power consumption and improved system bandwidth [1,2,3,4]
We studied the origins of the Through silicon via (TSV) leakage, focusing on the TSV etch process parameters and the intrinsic defects in Si substrate used for fabrication
EDX, respectively, Cu was found in the crack, leading to TSV leakage, which was attributed to the non-ideal TSV etch process and the intrinsic defects in the Si substrate used for fabrication
Summary
Smart mobile terminals have continuously driven the scaling of packaging density, especially in the vertical dimension with lowered power consumption and improved system bandwidth [1,2,3,4]. Various studies have shown the process readiness of 2.5D Si interposer [6,7,8] or embedded TSV as wide I/O [9], low-volume TSV technology is from via-last wafer-level packaging, which uses TSV with partial metal filling [10,11] This is a more cost-effective wafer-level packaging solution, it is not suitable for implementation in applications such as sensors, RF, and power devices that require good signal quality, robust reliability, and acceptable fabrication costs under squeezed package sizes (both for planar format and vertical thickness). Substrate defect, and thermal processing co-optimization, TSV leakage failure can be effectively suppressed, and such approaches present a promising solution for a reliable via-middle TSV embedded in CMOS for wafer-level packaging
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