Voltage Islands Research Articles

Improved energy harvesting by enhanced nonlinearities: New phenomena and experimental demonstration

This paper investigates a nonlinear piezoelectric energy harvesting system that enhances conversion of mechanical energy to electrical energy by integrating piezoelectric materials with a nonlinear system. The research simplifies a flexible beam with macro fiber composite (MFC) piezoelectric patches using a lumped-parameter approach and derives the dynamic equations of the system using the Lagrange equations. The incremental harmonic balance method (IHBM) is then employed to solve these equations, simulating the nonlinear dynamics involved in the harvested voltage. Key findings include the initial discovery of multiple voltage islands which are voltage jumps that improve energy conversion efficiency, confirmed by experimental data validating the IHBM simulations. The study reveals that these phenomena are due to the enhanced nonlinearities of the system, particularly the geometric nonlinearity caused by the spring k1 and the nonlinear magnetic force between magnets. Adjusting k1 allows the observation of multiple voltage islands, and increasing d0 results in a broad-frequency constant voltage, offering new insights. The research concludes that the nonlinear piezoelectric energy harvester can effectively convert vibration energy into electrical one, as demonstrated by successfully powering multiple light-emitting diodes (LEDs). Bifurcation diagrams illustrate the adaptability of the system, showing transitions among periodic, quasi-periodic, and chaotic states for different parameters.

Integer linear programming-based optimization methodology for reliability and energy-aware high-level synthesis

Continuous decrease in the transistor technology sizes has enabled much denser packaging of electronic components on chips, which has resulted in integrated circuits with lower costs and area. However, it has also given rise to new issues and challenges in the process of integrated circuit design, including higher vulnerability to soft errors. Modular hardware redundancy is a popular method for improving the reliability of a system against errors at a cost of increasing area and energy consumption. Voltage scaling methods can be employed to tackle high energy costs; however, this also negatively affects the circuit’s reliability and performance. Therefore, designing circuits with all these conflicting parameters is a very challenging task. In this study, we propose integer linear programming (ILP)-based high-level synthesis (HLS) methods to optimize both reliability and/or energy under the area and latency constraints. Our models employ full and partial duplication to improve the system reliability as long as the area constraint permits. They also utilize voltage islands as the energy reduction method of choice. What makes this problem even more interesting and complex is the fact that we use different versions of the same resources that have different area, latency, reliability, and energy values. Although this affects the execution time of the proposed methods, it also gives us more design options. We compared and showed the effectiveness of our methods against a genetic algorithm-based one on several HLS benchmarks. The ILP-based methods return the optimum results most of the time under the given time limits.

A stable voltage island-driven floorplanning with fixed-outline constraint for low power SoC

The multiple supply voltage technique is an effective method to address the challenge of chip power consumption. Voltage islands reduce the complexity of the power supply network during floorplanning of low-power systems-on-chip. In this paper, we present a voltage-island-driven floorplanning algorithm that considers fixed-outline constraints. First, we used the incremental shape curve addition algorithm to compute the best floorplan implementation for each floorplan solution represented by the normalized Polish expression. Second, a novel penalty function for modeling the fixed-outline constraint was integrated into the cost function to guide the simulated annealing (SA) search process. Finally, the insert after deletion operator optimizes the floorplan solution of the SA, such that the generated floorplan satisfies the strict fixed-outline constraint. Experimental results reveal that the proposed algorithm achieves a 94% floorplanning success rate under the strict constraint of 1% dead space percentage, and has better performance, including power and wire length.

Power aware floorplanning in multiple supply voltage domain

SummaryFloorplanning in this nano‐scale era involves consideration of various other objectives apart from minimizing wirelength in a fixed outlined region. In recent era of electronic devices, reducing power consumption is an important objective which can be achieved by multiple supply voltage island aware floorplanning. Optimizing power routing resource to simplify power planning while reducing voltage drop or IR drop (represented by maximum power length) is the major goal of the proposed work. Moreover, it has been observed that locations of blocks and power pads are important considerations for IR drop optimization. The proposed work hence concentrates on generating efficient floorplan with respect to wirelength, power routing resource, and IR drop. The proposed technique uses effective heuristics along with a SAT (Boolean satisfiability)‐based framework to generate efficient floorplan considering all factors. The experimental validation depicts good results with respect to power resource, wirelength, and voltage drop in a fixed outline framework.

Cross-Corner Delay Variation Model for Standard Cell Libraries

For timing closure of logic circuits, circuit designers must perform sign-offs on a variety of process, voltage, and temperature (PVT) conditions. Designs of advanced logic circuits involve a multitude of voltage islands and operating modes, each of which requires delay characterizations at nearby PVT corners. Furthermore, advanced technologies nodes suffer from corner explosion : while the impact of PVT variations is being exacerbated, process variations are also diversifying, increasing the number of operating conditions exponentially. This paper revisits the importance of cross-corner timing estimations and proposes a delay variation model to mitigate such corner explosion. Our objective is to reduce PVT corner characterization effort for timely static timing analysis on an exploding number of operating conditions. Our proposed Decomposed Propagation Vector Variation Model (DPVVM) decomposes propagation delay and timing constraints into the driving by the receiver cell and its driver cell; by scaling them separately, delay characterization effort is reduced to a fraction of time while realizing accurate timing estimations. We also propose Multi-Dimension Recomposition (MDR) scheme, which exploits a multitude of pre-characterized corners to further improve the consistency of cross-corner timing estimations. As a result, with only 8.0% of a corner characterization effort compared to the full-characterization, DPVVM combined with MDR achieves overall cross-corner timing estimation errors of 4.8% and 5.6% for single cells and complex logic circuits—or improvements of 69% and 61% over the conventional derating method, respectively. Our proposed method’s characterization overhead is 11% over the conventional derating method; the overhead is marginal, accounting for only 0.76% of a full-characterization time.

Research on neutral point grounding mode and single-phase earth fault location of medium voltage island microgrid

For medium voltage islanding microgrid, the voltage clamp of the main network neutral arc suppression coil or small resistance is lost. Multiple PTs parallel operation will occur because different entities of a microgrid independently measure the voltage. It is necessary to consider the influence of multi PTs ferroresonance on the neutral grounding mode of islanding microgrid. The neutral point ungrounded, neutral point grounded by arc suppression coil and neutral point grounded by small resistance are analyzed respectively, considering multi PTs ferroresonance and single-phase earth fault location, it is determined that the islanded microgrid adopts neutral point grounded by small resistance. On this basis, the zero sequence current distribution is used to locate the single-phase earth fault. Finally, a simulation example is built to verify the correctness of the proposed method.

Enabling Energy-Efficient and Reliable Neural Network via Neuron-Level Voltage Scaling

With the platforms of running deep neural networks (DNNs) move from large-scale data centers to handheld devices, power emerge as one of the most significant obstacles. Voltage scaling is a promising technique that enables power saving. Nevertheless, it raises reliability and performance concerns that may undesirably deteriorate NNs accuracy and performance. Consequently, an energy-efficient and reliable scheme is required for NNs to balance the above three aspects with satisfied user experience. To this end, we propose a neuron-level voltage scaling framework called NN-APP to model the impact of supply voltages on NNs from output accuracy (A), power (P), and performance (P) perspectives. We analyze the error propagation characteristics in NNs at both inter- and intra-network layers to precisely model the impact of voltage scaling on the final output accuracy at neuron-level. Furthermore, we combine a voltage clustering method and the multi-objective optimization to identify the optimal voltage islands and apply the same voltage to neurons with similar fault tolerance capability. We perform three case studies to demonstrate the efficacy of the proposed techniques.

Optimizing FPGA Logic Circuitry for Variable Voltage Supplies

Unlike central processing units (CPUs), field-programmable gate arrays (FPGAs) have conventionally been powered with a fixed supply voltage ( $V_{\text {dd}}$ ). However, recent efforts have shown that adopting dynamic voltage scaling reduces FPGA power consumption significantly. In this article, we analyze the delay sensitivity of different FPGA circuit elements to supply voltage changes and determine that conventional lookup table (LUT) designs greatly impact variable ${V_{\text {dd}}}$ operation. To build FPGAs with lower delay sensitivity to ${V_{\text {dd}}}$ , we propose several new LUT designs, including gate boosting the LUT, decoding the slowest two inputs of the LUT, and using separate voltage islands for the FPGA LUTs and routing. Our fastest proposed design (decode-driver island) reduces the area-delay product of the FPGA logic plus routing tile compared to a conventional design by 12% and 52% at ${V_{\text {dd}}}$ values of 0.8 V (the nominal voltage) and 0.6 V, respectively. Since our proposed FPGA tile designs are faster and have lower delay sensitivity to voltage, they offer better ${\text {Energy-Delay} {{^{\mathrm{ 2}}}}}$ product ( ${\text {ED} {{^{\mathrm{ 2}}}}}$ ) than that of the baseline at nominal ${V_{\text {dd}}}$ and below. Our decode-driver-island FPGA achieves a 26% ${\text {ED} {{^{\mathrm{ 2}}}}}$ reduction over the conventional design at the most efficient ${\text {ED} {{^{\mathrm{ 2}}}}}$ operating point.

Multi-Level Approximate Accelerator Synthesis Under Voltage Island Constraints

Approximate computing forms a promising paradigm shift for energy efficient design by aggressively decreasing power consumption of inherently error-tolerant applications. However, approximate computing architectures exacerbate the design complexity due to the diversity of inexact techniques and their impact on final circuit implementations. In this brief, we introduce approximate accelerator synthesis, which enables the design of power-optimized inexact circuits under error bound constraints, by leveraging the incorporation of diverse multi-level approximate techniques. We show the high efficiency of adopting multi-level approximation techniques and present a systematic approach for integrating multi-level approximation in hardware accelerator synthesis under error bound and voltage island constraints.

Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era

In this paper, we study the impact of the idle/dynamic power consumption ratio on the effectiveness of a multi-Vdd/frequency manycore design. We propose a new tool called LVSiM (a Low-Power and Variation-Aware Manycore Simulator) to carry out the experiments. It is a novel manycore simulator targeted towards low-power optimization methods including within-die process and workload variations. LVSiM provides a holistic platform for multi-Vdd/frequency voltage island analysis, optimization, and design. It provides a tool for the early design exploration stage to analyze large-scale manycores with a given number of cores on 3D-stacked layers, network-on-chip communication busses, technology parameters, voltage and frequency values, and power grid parameters, using a variety of different optimization methods. LVSiM has been calibrated with Sniper/McPAT at a nominal frequency, and then the energy-delay-product (EDP) numbers were compared after frequency scaling. The average error is shown to be 10% after frequency scaling, which is sufficient for our purposes. The experiments in this work are carried out for different Idle/Dynamic ratios considering 1260 benchmarks with task sizes ranging from 4000 to 16 000 executing on 3200 cores. The best configurations are shown to produce on average 20.7% to 24.6% EDP savings compared to the nominal configuration. Traditional scheduling methods are used in the nominal configuration with the unused cores switched off. In addition, we show that, as the Idle/Dynamic ratio increases, the multi-Vdd/frequency approach becomes less effective. In the case of a high Idle/Dynamic ratio, the minimum EDP can be achieved through switching off unused cores as opposed to using a multi-Vdd/frequency approach. This conclusion is important, especially in the dark-silicon era, where switching cores on and/or off as needed is a common practice.

Module Based Floorplanning Methodology to Satisfy Voltage Island and Fixed Outline Constraints

Multiple supply voltage is the most prevalent method for low power reduction in the design of modern Integrated circuits. Floorplanning process in this design performs positioning of functional blocks in the layout satisfying both fixed outline and voltage island constraints. The floorplans while satisfying these two significant constraints causes significant rise in wirelength and congestion. In this paper, a congestion and wirelength aware floorplanning algorithm is proposed which allows effective placement of functional blocks in the layout to satisfying fixed outline and voltage island constraints simultaneously. To perform voltage island floorplanning, the proposed algorithm uses Skewed binary tree representation scheme to operate the functional blocks in its predefined voltage level. The proposed methodology determines the feasible dimensions of the functional blocks in the representation which aids the placement process for the reduction of congestion and wirelength. With these optimal dimensions of the functional blocks, floorplanning is also performed for the layouts of aspect 1:1, 2:1, and 3:1, to evaluate the ability of proposed algorithm for satisfying the fixed outline constraint. The proposed methodology is implemented in the layout of InternationalWorkshop on Logic and Synthesis (IWLS) benchmarks circuits for experimental purpose. The resulting floorplans were iteratively optimized for optimal reduction of wirelength and congestion. Experimental results show that the proposed methodology outperforms existing state-of-the-art approaches in wirelength reduction by about 18.65% and in congestion reduction by around 63%, while delivering the 30.35% power consumption.

Energy and Reliability Improvement of Voltage-Based, Clustered, Coarse-Grain Reconfigurable Architectures by Employing Quality-Aware Mapping

An energy–quality scalable coarse grain reconfigurable architecture (CGRA) based on the voltage overscaling (VOS) technique is presented. The approximation level of each processing element (PE) in the CGRA is determined by the applied VOS-determined voltage level. By employing the technique, the architecture may be configured for accurate or approximate modes of computation depending on a user-specified output quality-of-service target for a given application. More precisely, operating voltages used for performing various operations in the application dataflow graph are minimized subject to the output quality constraint by using an energy–quality tradeoff algorithm. To make the hardware implementation of the scheme more efficient, PEs are clustered into groups of (e.g., $3\times 1$ and $2\times 1$ ) voltage islands. To assess the efficacy of the proposed method in improving the power (energy) consumption and reliability of CGRAs, different combinations of minimum output quality constraints, voltage levels, and cluster sizes for several benchmarks are studied. Simulation results indicate considerable reductions in energy consumption (up to 43%) and aging rate (up to 73%) when compared with the conventional CGRA with perfect output quality (i.e., with no approximate computations).

A Modified Algorithm for Voltage Assignment and Floorplanning of SOC Designs

Background/Objectives: Dynamic Power reduction has become a very important issue in the design of System on Chip (SOC). One of the methods for reduction is use of multiple supply voltage (MSV). In this MSV design, the modules are placed in the contiguous region such that modules of same operating voltage are placed in a same region. Such regions are called as Voltage Island. In this process, voltage assignment is followed by floor planning to avoid geometric constraints and physical information of the design. But increase in number of voltage island causes increase in number of level shifters between voltage islands. In this paper, we consider the Intellectual Property (IP) core based Voltage Island driven floorplanning problem including voltage island reduction. Voltage island reduction is carried over by matching algorithm. Methods/Statistical Analysis: The proposed matching algorithm constructs a graph G consisting of vertices as Voltages Island and edges as connectivity between Voltage Islands. The proposed matching algorithm takes care of number of modules and interconnects in between Voltage Island while contracting the vertices. Findings: The result of proposed matching algorithm is taken as candidate solution represented by Sequence Pair technique, for floorplanning. A new genetic algorithm based optimization is proposed to give the best solution of floorplan which reduces the dynamic power. The proposed algorithms are compared with two approaches such as partitioning the modules on the critical path and partitioning the modules of same operating voltage. Experimental results show that our proposed algorithm for voltage Island reduction and floorplanning minimizes the number of level shifters and overall Dynamic Power of circuit. Applications/Improvements: The proposed algorithm plays a significant role in the developing CAD software for the SOC Design. Our future work is on developing a suitable data structure for the floorplanning for multiple voltage design which includes IR drop in power rails as constraint. We also planned to focus this issue of multiple voltage design towards 3D ICs.

Multi-supply voltage (MSV) driven SoC floorplanning for fast design convergence

With the ever-increasing power demands of consumer electronics and portable devices, multi-supply voltage (MSV) technique is supposed as one of the direct and effective ways for power optimization in SoC designs. To realize MSV implementation, procedures such as voltage assignment, voltage island partitioning and level shifters (LSs) placement should be considered simultaneously during the floorplanning stage. Although many works addressed the MSV-driven design problem, few of them actually took account of LS placement, which makes the generated results may limit the potential applications. Furthermore, existing design frameworks are often very computationally expensive, and it is not beneficial to shorten the time to market. In this paper, we present an MSV-driven SoC floorplanning framework for fast design convergence. Several techniques are proposed and integrated into an efficient and flexible non-randomized floorplanning algorithm. Firstly, to reserve the desired deadspace for the placement of LSs, the netlist is modified by assigning virtual LSs in the nets. Secondly, a heuristic based voltage assignment method is presented for accuracy and execution time trade-off. Thirdly, different from previous works which do voltage assignment without physical information feedback, an inner loop is built between voltage assignment and LS placement under the constraints of both timing and physical layout. Experimental results on Gigascale Systems Research Center (GSRC) benchmark suites indicate the proposed approach can improve power saving by 12%, CPU time by 48% with 4% area increase.

Energy and Peak Power Efficiency Analysis for the Single Voltage Approximation (SVA) Scheme

Energy efficiency is an important issue in computing systems and operating within a safe power budget is a necessary constraint. This paper presents a simple and practical solution both for energy minimization and peak power reduction, called Single Voltage Approximation (SVA) scheme, for periodic real-time tasks on multicore systems with a shared supply voltage in a voltage island. SVA is inspired by the Single Frequency Approximation (SFA) scheme, in which all the cores in the island run at a single voltage and frequency such that all tasks can meet their deadlines. In SVA, all the cores in the island are also executed at the same single voltage as in SFA. However, the frequency of each core is individually chosen, such that the tasks in each core can meet their deadlines, but without running at unnecessarily high frequencies. Thus, all the cores are executing tasks all the time and there is no need for any Dynamic Power Management (DPM) technique for reducing the energy consumption for idling. For task partitioning, SVA is combined with the Double Largest Task First (DLTF) partitioning scheme. Most importantly, this paper provides comprehensive analysis for combining DLTF and SVA, deriving its worst-case behavior both for energy minimization and peak power reduction, compared against the optimal solutions. Our analysis shows that, depending on the hardware, the energy consumption by combining DLTF and SVA is at most 1.95 (2.21, 2.42, and 2.59, respectively), compared to the optimal solutions, when the voltage island has up to 4 (8, 16, and 32, respectively) cores, which outperforms the worst-case factors of SFA when the cores fail to sleep efficiently. For peak power reduction, due to running at slower frequencies, combining DLTF and SVA always outperforms SFA, both in average and corner cases. Finally, we extend our analysis considering multicore systems with discrete voltage and frequency pairs and multiple voltage islands.

Energy efficient scheduling of real-time tasks on multi-core processors with voltage islands

This paper studies energy efficient scheduling of periodic real-time tasks on multi-core processors with voltage islands, in which cores are partitioned into multiple blocks (termed voltage islands) and each block has its own power source to supply voltage. Cores in the same block always operate at the same voltage level, but can be adjusted by using Dynamic Voltage and Frequency Scaling (DVFS). We propose a Voltage Island Largest Capacity First (VILCF) algorithm for energy efficient scheduling of periodic real-time tasks on multi-core processors. It achieves better energy efficiency by fully utilizing the remaining capacity of an island before turning on more islands or increasing the voltage level of the current active islands. We provide detailed theoretical analysis of the approximation ratio of the proposed VILCF algorithm in terms of energy efficiency. In addition, our experimental results show that VILCF significantly outperforms the existing algorithms when there are multiple cores in a voltage island.

Energy Efficiency on Multi-Core Architectures with Multiple Voltage Islands

Efficient and effective system-level power management for multi-core systems with multiple voltage islands is necessary for next-generation computing systems. This paper considers energy efficiency for such systems, in which the cores in the same voltage island have to be operated at the same supply voltage level. We explore how to map given task sets onto cores, so that each task set is assigned and executed on one core and the energy consumption is minimized. Due to the restriction to operate at the same supply voltage in a voltage island, different mappings will result in different energy consumptions. By using the simple single frequency approximation scheme (SFA) to decide the voltages and frequencies of individual voltage islands, this paper presents the approximation factor analysis (in terms of energy consumption) for simple heuristic algorithms, and develops a dynamic programming algorithm, which derives optimal mapping solutions for energy minimization when using SFA. We experimentally evaluate the running time and energy consumption performance of these algorithms on Intel's single-chip cloud computer (SCC). Moreover, we conduct simulations for hypothetical platforms with different number of voltage islands and cores per island, also considering different task partitioning policies.

New Thermal-Aware Voltage Island Formation for 3D Many-Core Processors

The power consumption of 3D many-core processors can be reduced, and the power delivery of such processors can be improved by introducing voltage island (VI) design using on-chip voltage regulators. With the dramatic growth in the number of cores that are integrated in a processor, however, it is infeasible to adopt per-core VI design. We propose a 3D many-core processor architecture that consists of multiple voltage clusters, where each has a set of cores that share an on-chip voltage regulator. Based on the architecture, the steady state temperature is analyzed so that the thermal characteristic of each voltage cluster is known. In the voltage scaling and task scheduling stages, the thermal characteristics and communication between cores is considered. The consideration of the thermal characteristics enables the proposed VI formation to reduce the total energy consumption, peak temperature, and temperature gradients in 3D many-core processors.

Does the Sharing of Execution Units Improve Performance/Power of Multicores?

Several studies and recent real-world designs have promoted sharing of underutilized resources between cores in a multicore processor to achieve better performance/power. It has been argued that when utilization of such resources is low, sharing has a negligible impact on performance while offering considerable area and power benefits. In this article, we investigate the performance and performance/watt implications of sharing large and underutilized resources between pairs of cores in a multicore. We first study sharing of the entire floating-point datapath (including reservation stations and execution units) by two cores, similar to AMD’s Bulldozer. We find that while this architecture results in power savings for certain workload combinations, it also results in significant performance loss of up to 28%. Next, we study an alternative sharing architecture where only the floating-point execution units are shared, while the individual cores retain their reservation stations. This reduces the highest performance loss to 14%. We then extend the study to include sharing of other large execution units that are used infrequently, namely, the integer multiply and divide units. Subsequently, we analyze the impact of sharing hardware resources in Simultaneously Multithreaded (SMT) processors where multiple threads run concurrently on the same core. We observe that sharing improves performance/watt at a negligible performance cost only if the shared units have high throughput. Sharing low-throughput units reduces both performance and performance/watt. To increase the throughput of the shared units, we propose the use of Dynamic Voltage and Frequency Boosting (DVFB) of only the shared units that can be placed on a separate voltage island. Our results indicate that the use of DVFB improves both performance and performance/watt by as much as 22% and 10%, respectively.

Energy Efficiency Analysis for the Single Frequency Approximation (SFA) Scheme

Energy-efficient designs are important issues in computing systems. This article studies the energy efficiency of a simple and linear-time strategy, called the Single Frequency Approximation (SFA) scheme, for periodic real-time tasks on multicore systems with a shared supply voltage in a voltage island. The strategy executes all the cores at a single frequency to just meet the timing constraints. SFA has been adopted in the literature after task partitioning, but the worst-case performance of SFA in terms of energy consumption incurred is an open problem. We provide comprehensive analysis for SFA to derive the cycle utilization distribution for its worst-case behaviour for energy minimization. Our analysis shows that the energy consumption incurred by using SFA for task execution is at most 1.53 (1.74, 2.10, 2.69, respectively), compared to the energy consumption of the optimal voltage/frequency scaling, when the dynamic power consumption is a cubic function of the frequency and the voltage island has up to 4 (8, 16, 32, respectively) cores. The analysis shows that SFA is indeed an effective scheme under practical settings, even though it is not optimal. Furthermore, since all the cores run at a single frequency and no frequency alignment for Dynamic Voltage and Frequency Scaling (DVFS) between cores is needed, any unicore dynamic power management technique for reducing the energy consumption for idling can be easily incorporated individually on each core in the voltage island. This article also provides an analysis of energy consumption for SFA combined with procrastination for Dynamic Power Management (DPM), resulting in an increment of 1 from the previous results for task execution. Furthermore, we also extend our analysis for deriving the approximation factor of SFA for a multicore system with multiple voltage islands.