A stable voltage island-driven floorplanning with fixed-outline constraint for low power SoC

Abstract

The multiple supply voltage technique is an effective method to address the challenge of chip power consumption. Voltage islands reduce the complexity of the power supply network during floorplanning of low-power systems-on-chip. In this paper, we present a voltage-island-driven floorplanning algorithm that considers fixed-outline constraints. First, we used the incremental shape curve addition algorithm to compute the best floorplan implementation for each floorplan solution represented by the normalized Polish expression. Second, a novel penalty function for modeling the fixed-outline constraint was integrated into the cost function to guide the simulated annealing (SA) search process. Finally, the insert after deletion operator optimizes the floorplan solution of the SA, such that the generated floorplan satisfies the strict fixed-outline constraint. Experimental results reveal that the proposed algorithm achieves a 94% floorplanning success rate under the strict constraint of 1% dead space percentage, and has better performance, including power and wire length.