Abstract
Floorplanning is an essential design step for hierarchical, building-module design methodology. Floorplanning provides early feedback that evaluates architectural decisions, estimates chip areas, and estimates delay and congestion caused by wiring. This chapter starts with the formulation of the floorplanning problem. After the problem formulation, the two most popular approaches to floorplanning, simulated annealing and analytical formulations, are discussed. The most popular floorplanning method resorts to the modeling of the floorplan structure and then optimizes the floorplan solutions with simulated annealing. Some modern floorplanning issues such as soft modules, fixed-outline constraints, and large-scale designs are also addressed. Normalized Polish expression, B*-tree, and sequence pair have been recognized as the most valuable representations because of their superior simplicity, effectiveness, efficiency, and flexibility. In additional to simulated annealing, analytical floorplanning approaches have shown their advantage in the effective wire length optimization; however, it is harder to handle the module overlaps and the fixed-outline constraint for such an approach. Floorplanning, considering both hard and soft modules, is also more challenging for the analytical approach. After floorplanning, all hard modules are fixed.
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