CHAPTER 11 - Placement

Abstract

This chapter discusses placement, which is the process of determining the locations of circuit devices on a die surface. It is an important stage in the very large-scale integration (VLSI) design flow, because it affects routability, performance, heat distribution, and to a less extent, power consumption of a design. Traditionally, it is applied after the logic synthesis stage and before the routing stage. The chapter begins with an introduction to the placement stage. Various placement problem formulations are discussed. Partitioning-based approach, simulated annealing approach, and analytical approach for global placement are presented. After that, legalization and detail placement algorithms are described. Since the advent of deep submicron process technology around the mid-1990s, interconnect delay, which is largely determined by placement, has become the dominating component of circuit delay. As a result, placement information is essential, even in early design stages, to achieve better circuit performance. In recent years, placement techniques have been integrated into the logic synthesis stage to perform physical synthesis and into the architecture design stage to perform physical-aware architecture design. The chapter concludes with a discussion of other placement approaches and useful resources to placement research.