CHAPTER 3 - Design for testability

Abstract

This chapter reviews the basic design for testability (DFT) concepts and methods for performing testability analysis. Scan design, the most widely used structured DFT method, is discussed, including popular scan cell designs, scan architectures, and at-speed clocking schemes. DFT has become an essential part for designing very large-scale integration (VLSI) circuits. The most popular DFT techniques in use today for testing the digital portion of the VLSI circuits include scan and scan-based logic built-in self-test (BIST). Both techniques have proved to be quite effective in producing testable VLSI designs. In addition, test compression, a supplemental DFT technique for scan, is growing in importance for further reduction in test data volume and test application time during manufacturing test. To provide readers with an in-depth understanding of the most recent DFT advances in scan, logic BIST, and test compression, the chapter covers a number of fundamental DFT techniques to facilitate testing of modern digital circuits. These techniques are required to improve the product quality and reduce the defect level and test cost of a digital circuit, while at the same time simplifying the test, debug, and diagnosis tasks. BIST pattern generation and output response analysis schemes are discussed with a number of logic BIST architectures for in-circuit self test. Finally, a number of test compression circuit structures for test stimuli compression and test response compaction are presented.