Chapter 2 - Digital Test Architectures

Abstract

Scan and logic built-in self-test (BIST) are currently the two most widely used design-for-testability (DFT) techniques for ensuring circuit testability and product quality. This chapter presents a number of fundamental and advanced logic BIST architectures that allow the digital circuit to perform self-test on-chip, on-board, or in-system. Test compression architectures designed to reduce test data volume and test application time are discussed. This includes a description of advanced low-power and at-speed test compression architectures practiced in industry. Additionally this chapter explores promising random-access scan architectures devised to further reduce test power dissipation and test application time while retaining the benefits of scan and logic BIST. Furthermore, logic BIST is of growing importance in very-large-scale integration (VLSI) manufacturing, when combined with its major advantages of performing on-chip self-test and in-system remote diagnosis. It has been anticipated that for VLSI designs at 65 nanometers and below, logic BIST and low-power testing will gain more industry acceptance. Although the Self-Testing Using MISR and Parallel SRSG-based architecture is the most popular logic BIST architecture now practiced for scan-based designs, the efforts required to implement the BIST circuitry and the loss of the fault coverage for using pseudo-random patterns have prevented the BIST architecture from being widely used across all industries.