Abstract
As complementary metal oxide semiconductor (CMOS) processes evolve, design for manufacturability (DFM) and design for yield (DFY) will become increasingly important, and their interaction with design for testability (DFT) will also become critical. In this chapter the combination of these and other effects is classified as design for excellence (DFX). A key aspect of DFX is its ability to cope with ever increasing amounts of variability that will be encountered with reduced feature sizes. Furthermore, overall yield is composed of five subcategories: systematic yield, parametric yield, defect-related yield, design-related yield, and test-related yield. The demise of Moore's law and CMOS scaling has been predicted for more than 20 years, but innovation has so far trumped the detractors. The effective use of design in order to improve manufacturability and yield has always been a competitive advantage for those who have tried it and will continue to be a vital component of IC design and manufacturing. As DFX evolves it will absorb new areas, including variability, reliability, and power management.
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