Chapter 8 - Coping with Physical Failures, Soft Errors, and Reliability Issues

Abstract

Advances in semiconductor manufacturing technology have allowed the integration of a billion transistors in a nanometer design. This chapter presents several promising techniques for testing nanometer designs that can cope with physical failures caused by signal integrity, defects, and process variations during manufacturing. These test techniques are developed for reliability screen or defective parts per million reductions. A few include on-chip hardware for stressing or special reliability measurements. These defect avoidance techniques are generally referred to as design for manufacturability (DFM). With the process node now scaling down to 65 nanometers and below, DFM alone is not enough. Many new defect mechanisms, such as copper-related defects and defects as a result of optical effects, become much more likely. Any single-event upsets can increase logic and memory soft error rates. It is thus becoming crucial to ensure that the chips can still function at the end system in the presence of these defects and soft errors, especially when the chips are to be installed into airplanes, pacemakers, or cars for safety-critical concerns. This chapter also covers a number of error-resilient and defect-tolerant designs embedded on-chip to tolerate soft errors and defects. Although these schemes may require additional area overhead, they pave the way to develop more advanced error-resilient and defect-tolerant scan and logic BIST architectures to cope with the physical failures of the nanometer age.