Abstract
SummaryFloorplanning in this nano‐scale era involves consideration of various other objectives apart from minimizing wirelength in a fixed outlined region. In recent era of electronic devices, reducing power consumption is an important objective which can be achieved by multiple supply voltage island aware floorplanning. Optimizing power routing resource to simplify power planning while reducing voltage drop or IR drop (represented by maximum power length) is the major goal of the proposed work. Moreover, it has been observed that locations of blocks and power pads are important considerations for IR drop optimization. The proposed work hence concentrates on generating efficient floorplan with respect to wirelength, power routing resource, and IR drop. The proposed technique uses effective heuristics along with a SAT (Boolean satisfiability)‐based framework to generate efficient floorplan considering all factors. The experimental validation depicts good results with respect to power resource, wirelength, and voltage drop in a fixed outline framework.
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