Voltage Drop Aware Power Pad Assignment and Floorplanning for Multi-voltage SoC Designs

Abstract

Multi-voltage technique is an effective way of power saving in system-on-a-chip (SoC) designs. However, as the technology nodes continue to shrink, the voltage drop constraint in multiple power domains presents serious obstacles in power/ground (P/G) network design of wire-bonding package. In this paper, a voltage drop aware power pad assignment and floor planning method for multi-voltage SoC designs is proposed. In order to reduce the voltage drop, we develop a fast method to calculate the location of power pad for each power domain based on the spring model. During floor planning iterations, a static voltage drop analysis is performed to update the voltage drop distribution, and then number of violation nodes in the P/G network is obtained. To speed up the floor planning algorithm, instead of time-consuming matrix computation to obtain voltage drops, we use the weighted distance from blocks to power pads as an optimization objective. Experimental results on GSRC benchmark suites indicate that the proposed approach generates an optimized placement of power pads and floor planning of blocks.