Exploring more efficient architectures for Multiple Dynamic Supply Voltage designs

Abstract

Multiple Dynamic Supply Voltage (MDSV) is a technique that focuses on reducing the dynamic power. This technique is an evolution of the Multiple Supply Voltage (MSV). MSV and MDSV introduce some difference on traditional physical synthesis due to the different voltage operations of each region in the design. To convert the voltage among regions supplied by different voltages, these techniques insert a Level Shifter (LS) circuit. As a penalty consequence, traditional LS circuits insert a delay and extra power consumption in the design. The dynamical behavior of MDSV designs has brought a new condition, where LS inserted in the circuit can be in an idle state temporally. This work presents a new architecture to reduce the power consumption and delay, bypassing the LS. The architecture explores an alternative path to current flow in the cases that LS is idle. With this new approach we reduce up to 15% of power consumption and up to 75% and 15% of delay.