On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits

Abstract

On-chip power distribution grids with multiple supply voltages are discussed in this paper. Two types of interdigitated and paired power distribution grids with multiple supply voltages and multiple grounds are presented. Analytic models are also developed to estimate the loop inductance in four types of proposed power delivery schemes. Two proposed schemes, fully and pseudo-interdigitated power delivery, reduce power supply voltage drops as compared to conventional interdigitated power distribution systems with dual supplies and a single ground by, on average, 15.3% and 0.3%, respectively. The performance of the proposed on-chip power distribution grids is compared to a reference power distribution grid with a single supply and a single ground. The voltage drop in fully interdigitated and fully paired power distribution grids with multiple supplies and multiple grounds is reduced, on average, by 2.7% and 2.3%, respectively, as compared to the voltage drop of an interdigitated power distribution grid with a single supply and a single ground. The proposed power distribution grids are a better alternative to a single supply voltage and a single ground power distribution system. On-chip resonances in power distribution grids with decoupling capacitors are intuitively explained in this paper, and circuit design implications are provided. It is also noted that fully interdigitated and fully paired power distribution grids with multiple supply voltages and multiple grounds are recommended to decouple power supply voltages.