VLSI Memory Research Articles

A Novel Two Level Edge Activated Carry Save Adder for High Speed Processors

In today’s increasing demand of higher integration levels of VLSI and ULSI processors memory capacity and ALU efficiency plays a critical role in designing. The chip-size of memory depends on number of Flip-Flop’s (FF) which are the micro cells to store binary values. An efficient adder is always a parameter to estimate the cost effectiveness of multipliers used by ALU. In this paper the authors focuses on frequency clock utilization and also on low power consumption. It presents a novel Carry Save Adder (CSA) combined with the concept of two level clock triggering for high speed integrated circuits. The authors proposes a new Two Level Edge Triggered (TLET) FF’s built with 14Transistors (14T) and 12Transistors (12T), efficient in terms of switching power dissipation and delay in this paper. The innovative idea deals with CSA 14T and 12T which is compared in terms of Switching Power Dissipation (SPD) from 0.8V to 2.0V. The difference in SPD from 0.8V to 2.0V supply voltage analysis is 132.0nWatts for CSA using 16T FFs, 85.6nWatts for CSA using 14T and only 70.3nWatts for CSA using 12T FFs. In this paper, there is full utilization of clock signal.

Effects of multi-context information recorded at different regions in holographic polymer-dispersed liquid crystal on optical reconfiguration

A holographic polymer-dispersed liquid crystal (HPDLC) memory to record multi-context information for an optically reconfigurable gate array is formed by constructing a laser illumination system to implement successive laser exposures at different small regions in a glass cell filled with LC composites. The context pattern arrangements for circuit information are designed in a 3 × 3 in.2 photomask by electron beam lithography, and they are recorded as laser interference patterns at nine regions separated in an HPDLC sample by a laser interferometer composed of movable pinhole and photomask plates placed on motorized stages. The multi-context information reconstructed from the different regions in the HPDLC is written to a photodiode array in a gate-array VLSI by switching only the position of laser irradiation using the displacement of the pinhole plate under the control of a personal computer (PC). The effects of multi-context information recorded at different regions in the HPDLC on optical reconfiguration are discussed in terms of the optical system composed of ORGA VLSI and HPDLC memory. The internal structures in the HPDLC memory formed by multi-context recording are investigated by scanning electron microscopy (SEM) observation, and the configurations composed of LC and polymer phases are revealed at various regions in the HPDLC memory.

(Invited) Storage Class Memory and NAND Flash Memory Hybrid Solid-State Drives (SSD)

SSDs and emerging storage class non-volatile semiconductor memories (SCM) such as PCRAM, FeRAM, ReRAM and MRAM have enabled innovations in various nano-scale VLSI memory systems for personal computers, multimedia applications and enterprise servers. This paper provides a comprehensive review on state-ofthe-art data management technologies of storage class memory and NAND flash memory hybrid solid-state drives (SSDs)

Highly reliable, high speed and low power NAND flash memory-based Solid State Drives (SSDs)

SSDs and emerging storage class non-volatile semiconductor memories such as PCRAM, FeRAM, RRAM and MRAM have enabled innovations in various nano-scale VLSI memory systems for personal computers, multimedia applications and enterprise servers. This paper provides a comprehensive review on various state-of-the-art memory system architectures and related memory circuits for the highly reliable, high speed and low power NAND flash memory based SSDs.

Design and analysis of a self-testing-and-repairing random access memory “STAR–RAM” with error correction

This paper presents the philosophy and design of a fault-tolerant dynamically-reconfigurable random access memory (RAM) system with a built-in Self-Testing-And-Repairing “STAR” engine. The STAR engine, supported by SEC–DED capability, provides on-line fault detection, correction, analysis and repair without destroying useful data stored in the memory. Reliability analysis of the presented system has been accomplished using a SMART simulation approach [1], and results show significant reliability enhancement over SEC–DED RAM designs. The memory system employs a hardware parallel address-comparison mechanism for rapid processing of incoming addresses during normal read/write operations to minimize memory access delay. The flexible STAR architecture and the low hardware overhead enables utilization of the proposed approach in VLSI memory chips as well as in WSI and large memory modules.

OPTICALLY ACCESSED ELECTRONIC MEMORY

Abstract We describe the potential impact of liquid crystal technology when integrated with VLSI memory to allow optical access, an approach currently under development within this laboratory. Such a technology, known as opto-RAM, may increase the data rate to and from electronic memory by at least two orders-of-magnitude when compared to an all-electronic read/write.

Device processing and integration of ferroelectric thin films for memory applications

This review deals with the tasks involved in integrating ferroelectric thin films for memory applications. Main emphasis is put on process integration. Some of the results presented (especially dry etching ones) come from the European ESPRIT project called FELMAS. The compatibility of CMOS devices and ferroelectric capacitors is discussed and main issues toward the development of VLSI memories, are outlined.

Electromigration and stress-induced voiding in fine Al and Al-alloy thin-film lines

Physical phenomena underlying failure due to electromigration and stress-induced voiding in fine Al and Al-alloy thin-film conducting lines are examined in the context of accelerated testing methods and structures. Aspects examined include effects due to line isolation (the absence of reservoirs at conductor ends), solute and precipitate phenomena, conductor critical (Blech) length, microstructure, film deposition conditions, and thermal processing subsequent to film deposition. Emphasis is on the isolated, submicron-wide, Al(Cu)-based thin-film interconnection lines of IBM VLSI logic and memory chips.

An Overview of VLSI Memory Yield Management by Injection of Fault Tolerance

Presents an overview of memory chip yield enhancement techniques by injection of fault tolerance. As memory chips are more prone to defects, the yield of good chips from a silicon wafer governs their production cost. As shown, most fault tolerance techniques assume a relatively large area overhead which results in additional costs in terms of the silicon used as well as the lower number of chips/wafers produced. Proper management of fault tolerance, as by the word redundancy approach, adds an almost negligible area overhead to the chip and leads to considerably higher yields.

A new built-in self-repair approach to VLSI memory yield enhancement by using neural-type circuits

It is shown how to represent the objective function of the memory repair problem as a neural-network energy function, and how to exploit the neural network's convergence property for deriving optimal repair solutions. Two algorithms have been developed using a neural network, and their performances are compared with that of the repair most (RM) algorithm. For randomly generated defect patterns, a proposed algorithm with a hill-climbing capability successfully repaired memory arrays in 98% cases, as opposed to RMs 20% cases. It is demonstrated how, by using very small silicon overhead, one can implement this algorithm in hardware within a VLSI chip for built in self repair (BISR) of memory arrays. The proposed auto-repair approach is shown to improve the VLSI chip yield by a significant factor, and it can also improve the life span of the chip by automatically restructuring its memory arrays in the event of sporadic cell failures during the field use.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

VLSI failure analysis: A review

EBP (electron beam probing) and FIB (focused ion beam) applications to VLSI failure analysis are reviewed. The EBP system is segregated into three generations from a testing automation viewpoint. The first generation is a simple modification to SEM: SEM + beam blanking equipment for pulse beam generation, a simple pulse generator to stimulate the DUT (device under test), etc. The second generation is a more practical system, which includes a pulse generator to stimulate a more complex DUT, image processor, etc. The third one is an automatic or semi-automatic system, which combines with an LSI design database. FIB applications were segregated into microscopic cross-sectioning and in situ observation, preparation for further failure analysis, and aluminum grain observation. Three VLSI failure analysis examples concerning microscopic cross-sectioning and in situ observations are shown. One is a cross section of a VLSI memory, which failed during a high temperature life test. Another example is the cross section of a gate array, which failed in wafer sorting test because of a short circuit caused by a pinhole at the SiO 2 layer between the metal layer and the substrate. The other example is that of a VLSI gate array, which failed in the wafer sorting test because of an open circuit caused by process anomalies. As a preparation tool for further failure analysis, FIB has been mainly utilized for cutting and connecting metal lines when changing a circuit, making holes at an insulation layer for EBP, probing pad formation for mechanical probing and EBP, microscopic cross-sectioning for SEM observation, and marking for TEM (transmission electron microscope) observation. As an aluminum microstructure observation tool, FIB as SIM (scanning ion microscope) is shown to be useful, not only for qualitative aluminum grain observation, but also for quantitative aluminum grain orientation measurement. Individual failure analysis examples is shown, using photographs.

Structure of the test program for vlsi memory devices and its application

AbstractVLSI memories have been diversifying along with high density and high speed. With diversification, the evaluation test program also must handle each VLSI memory, and the efficiency of its generation is an important issue.In this paper, to evaluate diversifying VLSI memories, a program structure is described which can create evaluation test programs quickly for semiconductor test equipment, especially memory testers. The test program presented herein has a module structure consisting of utility groups for evaluation, a main program, and subroutine programs which describe the specific test conditions for each VLSI memory. Also, it can handle the evaluation of various VLSI memories with minimum programming.As a result of using this program structure for the evaluation test programs for 16 kinds of VLSI memories, it has been confirmed that the program development time can be reduced to one‐fifth that of the conventional method and the evaluation time can also be reduced by one hour.

Synergistic fault-tolerance for memory chips

The discovery of a principle of synergistic fault tolerance is described, and it is shown analytically why it occurs. The performance of its hardware implementation, in the form of a VLSI memory chip, is reported. An analysis of the error-correction scheme implemented in the hardware is presented, and limitations to the use of error-correcting codes for fault tolerance are explained. Methods for circumventing these limitations with the use of redundant circuits are discussed, analyzing the effect of bitline and wordline redundancy. The result of the analysis shows how the combination of error-correcting codes with redundant circuitry results in a fault-tolerance synergism. >

High throughput E-B test system for VLSI memories

Abstract This paper describes a new E-B test system which offers the fully automatic failure analysis for VLSI memory at the wafer level. This system consists of two principal functions; an auto-navigator to locate the failure area, and an E-B tester with voltage contrast imaging and logic state mapping. Every process of failure analysis is executed fully automatically. The test results from the LSI tester are analyzed and the possible failure areas are listed. Each area is automatically E-B tested in order and the real cause of the failure is determined. This system allows failure analysis at the wafer level and the analysis time is reduced one twentieth compared with the conventional E-B tester.

High-performance tantalum oxide capacitors fabricated by a novel reoxidation scheme

High-performance tantalum oxide capacitors with excellent reliability that were developed by a two-step oxidation scheme are discussed. An anodic reoxidation process is applied to the reactively sputter-deposited tantalum oxide films to make the densified oxide structure. The electrical and physical properties as well as the reliability of these two-step oxidized sputtered/anodized tantalum oxide films are shown to be much superior to those of conventional tantalum oxide films prepared by either anodization or sputtering alone. Capacitors made of the sputtered/anodized tantalum oxide film have greatly improved electrical properties and better reliability than anodized or sputtered tantalum oxide capacitors and are very useful for applications to high-capacity storage capacitors in future high-density VLSI memories. >

Repairability/unrepairability detection technique for yield enhancement of VLSI memories with redundancy

In this paper, a new approach to repairability/unrepairability detection for VLSI memory chips with redundancy is presented. An heuristic, yet efficient approach, is proposed. New conditions for detection are presented and fully analysed. These are based on a more accurate estimation of the regions of repairability and unrepairability. The main benefit of this approach is its practicality with respect to fast execution time and the improved ability to diagnose a VLSI redundant memory before the generation of the repair-solution. A new repair algorithm which utilizes a ternary tree approach is also presented.

A 68-ns 4-Mbit CMOS EPROM with high-noise-immunity design

In a VLSI memory, noise generated by its own operation is a serious problem. The noise disturbs data sensing, especially in EPROMs which have a single-ended sensing scheme. To develop high-density and high-speed EPROMs, it is necessary to solve the noise problems. Incorrect EPROM functions due to the noise are discussed. High-noise-immunity circuit techniques for stable data sensing and high-speed access time are proposed. These are divided bit-line layout, reference line with dummy bit lines, and a chip-enable transition detector. Using these circuit techniques and 0.8- mu m n-well CMOS technology, a 512 K*8-b CMOS EPROM was developed. A 68-ns access time was achieved. The die size is 5.62 mm*15.30 mm, and it is assembled in a 600-mil cerdip package.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Computer-simulated explosion of poly-silicide links in laser-programmable redundancy for VLSI memory repair

A computer model has been used to describe the temperature evolution of link targets as they are typically processed in laser programmable redundancy. Three such infrared laser simulations are described: (1) short-pulse polysilicon targets, (2) short-pulse TaSi/sub 2/-polysilicon targets, and (3) long-pulse TaSi/sub 2/-polysilicon targets. Reliability issues involved with each of these three laser target systems are discussed. Good correlation has been noted between the model results and two experiments involving ambient wafer temperature and long-pulse laser processing. The poly-silicide target is shown to present short-pulse infrared laser processing difficulties not encountered in a solid polysilicon link. These are caused by the strong optical absorption of the TaSi/sub 2/, the subsequent screening of deeper target material, and the high melting and vaporization temperatures of this silicide. The transparent top dielectric and the optical properties of solid and liquid silicon play important roles in the suggested reliability of the solid polysilicon link. Although the use of a long-pulse laser on poly-silicide targets appears to overcome some of the above-mentioned difficulties, subsequent reliability and performance degradation casts doubt on this technique for high-volume manufacturing. >

Explosion of poly-silicide links in laser programmable redundancy for VLSI memory repair

Laser programmable redundancy has been used in very large-scale memory devices to increase yields through the replacement of defective elements by spare rows or columns. The effect of scaling on the laser repair rate due to chip size and density increase in VLSI is discussed. The laser target link material systems that were used to implement redundancy in recent generations of DRAM and the laser pulse characteristics are described. Various laser explosion patterns in poly-silicide links are described, and the caused of their formation and their effects on repair rate are discussed. Several experiments of laser link explosion under various conditions were performed to compare the observed facts with a theoretical model. Good correlations have been obtained.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Material Development Challenges in High Density Pakaging of Advanced VLSI Memory Devices

AbstractAdvances in semiconductor memory storage technology are making possible the development of high density memory cards for hand held and portable product applications. This in turn is driving development of ever denser, ultra-thin component packages. Both materials and package design must be more robust in order for next generation packages to withstand surface mount reflow soldering stresses. Trade-offs among ercapsulant properties may be possible in view of new interconnect, die surface protection and leadframe design technologies which are being adopted for high density packaging. Materials and packaging engineers are challenged to capitalize on opportunities offered by these changes in order to optimize strength and moisture resistarnce in developing encapsulating materials for the new generation of packages.