Abstract
Abstract This paper describes a new E-B test system which offers the fully automatic failure analysis for VLSI memory at the wafer level. This system consists of two principal functions; an auto-navigator to locate the failure area, and an E-B tester with voltage contrast imaging and logic state mapping. Every process of failure analysis is executed fully automatically. The test results from the LSI tester are analyzed and the possible failure areas are listed. Each area is automatically E-B tested in order and the real cause of the failure is determined. This system allows failure analysis at the wafer level and the analysis time is reduced one twentieth compared with the conventional E-B tester.
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