Abstract
In today’s increasing demand of higher integration levels of VLSI and ULSI processors memory capacity and ALU efficiency plays a critical role in designing. The chip-size of memory depends on number of Flip-Flop’s (FF) which are the micro cells to store binary values. An efficient adder is always a parameter to estimate the cost effectiveness of multipliers used by ALU. In this paper the authors focuses on frequency clock utilization and also on low power consumption. It presents a novel Carry Save Adder (CSA) combined with the concept of two level clock triggering for high speed integrated circuits. The authors proposes a new Two Level Edge Triggered (TLET) FF’s built with 14Transistors (14T) and 12Transistors (12T), efficient in terms of switching power dissipation and delay in this paper. The innovative idea deals with CSA 14T and 12T which is compared in terms of Switching Power Dissipation (SPD) from 0.8V to 2.0V. The difference in SPD from 0.8V to 2.0V supply voltage analysis is 132.0nWatts for CSA using 16T FFs, 85.6nWatts for CSA using 14T and only 70.3nWatts for CSA using 12T FFs. In this paper, there is full utilization of clock signal.
Highlights
In present scenario, technology is evaluated by its computational procedures
In Carry Save Adder (CSA) using 12T TLETFF A and B are 6-bit wide inputs where A=B=‖100011‖ and Carry Input Cin=‘1‘ the logic circuit output sum is from S0 to S5 www.ijacsa.thesai.org which is equal to ―000111‖ and Cout= ̳1‘ .For the CSA implemented using 12T and 14T the clock frequency is equal to the frequency at which sum bits are generated
The delta change between maximum and minimum (0fF) power dissipation of 16T FF is 51μW, for 14T it is 44 μW and for 12T it is 37μW. switching power of 12TFF is reduced by 27.4% when compared to 16T FF. 14T FF‘s switching power is reduced by 13.5% when compared with 16T FF. 12T FF shows more percentage reduction in power when compared with 14T
Summary
Abstract—In today’s increasing demand of higher integration levels of VLSI and ULSI processors memory capacity and ALU efficiency plays a critical role in designing. In this paper the authors focuses on frequency clock utilization and on low power consumption. It presents a novel Carry Save Adder (CSA) combined with the concept of two level clock triggering for high speed integrated circuits. The authors proposes a new Two Level Edge Triggered (TLET) FF’s built with 14Transistors (14T) and 12Transistors (12T), efficient in terms of switching power dissipation and delay in this paper. The innovative idea deals with CSA 14T and 12T which is compared in terms of Switching Power Dissipation (SPD) from 0.8V to 2.0V.
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