VLSI Memory Research Articles

Leakage-current reduction in thin Ta/sub 2/O/sub 5/ films for high-density VLSI memories

Key techniques for applying Ta/sub 2/O/sub 5/ film to megabit-class MOS DRAMs are presented. A high-purity (4N and up) Ta sputtering target is developed to obtain high-purity Ta/sub 2/O/sub 5/ film. The leakage current in Ta/sub 2/O/sub 5/ film that is deposited using a clean sputtering system with this high-purity target is far lower than that of film deposited with a conventional target. A previous drawback of Ta/sub 2/O/sub 5/, the decrease of effective dielectric constant as thickness decreases, is solved by using Mo as an electrode material. The leakage current increase that results from using metal as a bottom electrode is suppressed by reducing the electrode asperity. MOS DRAMs of up to 16-Mb capacity can be attained without trench technology by using these techniques.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

On–chip multibit–test scheme for VLSI memories

AbstractTo reduce the time needed for testing VLSI memory chips, an on‐chip multibit‐test (MBT) scheme is proposed. The conditions for the test scheme and the relationship between the test mode and the memory array architecture (data bus structure, redundancy scheme, and so forth) are discussed. When the MBT mode is applied to the 1‐Mbit DRAM, the increase in the chip area and power consumption are minimized, and the test for a 256‐K bit device can be adopted to the memory array operating test. Using this technique, the time required for testing the device is reduced one‐half to one‐third.

A new soft-error-immune DRAM cell using a stacked CMOS structure

A new VLSI memory cell is proposed that offers high immunity to alpha-particle-induced soft errors and a cell area comparable to a one-transistor memory cell. This memory cell consists of a pair of complementary MOSFET's and one capacitor. The PMOSFET is formed in an SOI film over the NMOSFET. Since both storage capacitor nodes are kept electrically floating in retention periods and one storage capacitor node is formed in a thin SOI film, an alpha-particle hit does not destroy the stored charge of this memory cell. It is sufficient for an SOI-PMOSFET to provide only three orders of magnitude ON/OFF current ratio. Experimental memory cells were fabricated using polysilicon film as an SOI film. Measuring them confirmed the main effectiveness of this memory cell.

Titanium nitride local interconnect technology for VLSI

This paper reports on how the self-aligned titanium disilicide process, normally used to simultaneously reduce MOS gate and junction sheet resistances to less than 1 Ω/square, has been extended to provide a layer of local interconnect for VLSI CMOS applications. The local interconnect level has been realized by utilization of the titanium nitride (TIN) layer that forms during the gate and junction silicidation process. Normally the TiN layer is discarded, but in this process the 0.1-µm-thick TiN layer is patterned and etched to provide local connections between polysilicon gates and n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> and p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> junctions, with a sheet resistance of less than 10 Ω/ square. This is accomplished without area consuming contacts or metal straps, and without any extra deposition steps. In addition to providing a VLSI version of the buried-contact process, the technology permits the widespread use of self-aligned contacts and minimum geometry junctions. These features significantly reduce parasitic capacitance with the result that the signal propagation delay through a 1-µm CMOS inverter is decreased by 20- 25 percent. The TiN local interconnect process has been successfully demonstrated by the fabrication of a pseudo-static CMOS VLSI memory with nearly half a million 1-µm transistors. A full CMOS 16K SRAM has also been fabricated in which the TiN layer performs the gate to n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> and p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> junction cross-coupling function. Application of the technology to achieve a high-density full CMOS SRAM cell, that makes a 256K SRAM chip size of less than 80K mils <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> feasible with 1-µm design rules, is also discussed.

EB60: An advanced direct wafer exposure electron-beam lithography system for high-throughput, high-precision, submicron pattern writing

A high-throughput, high-precision e-beam direct writing system, the EB60, has been developed for both submicron VLSI memories and application specific integrated circuits (ASICs). The throughput is twenty and eighty 4-in. wafers per hour for 0.5 μm VLSI memories and 0.8 μm ASICs, respectively, with ±0.1 μm overlay accuracy. To achieve this performance, a novel drawing method and the following key subsystems were developed: (1) Vector beam scanning during continuous stage movement with an advanced three dimensional registration method, which has reduced overhead time and results in a well balanced system design. (2) Variable shaped beam electron optical column with 0.2 μm beam edge resolution at 2.0×1.5 (1.5×2.0) μm maximum beam size and a current density of up to 70 A/cm2. (3) High-speed beam deflection and dynamic focus system, including high-speed analog circuits, all-electrostatic deflectors, and an electrostatic dynamic focus lens. (4) Fast pattern controller, which executes 16 Mshot/s pattern data generation, and several data calculations for beam positioning error corrections and pattern writing during continuous stage movement. (5) High-speed precision ceramic XY stage and high-speed wafer handling mechanism which enables automatic exposure of 50 wafers. (6) Control software which is friendly to both operators and LSI designers. Through the coordination of the above subsystems, a lithography system with a high throughput and a wide range of applications has been developed.

4601034 Method and apparatus for testing very large scale integrated memory circuits

Apparatus for testing high density VLSI memory elements of a semiconductor chip having bit line connections to at least selected ones of which includes a parallel signature analyzer built onto the chip adjacent the memory elements and connected to at least some of them by the bit line connections. The parallel signature analyzer is configurable to apply selected signals onto the bit lines in one mode to enable test signals to be written into selected memory cells to generate preselected memory states therewithin. The parallel signature analyzer is also configurable, in another mode to read the states of the memory cells and to develop a signature of the states read to indicate whether the selectively applied signals were properly written into and read from the high density memory. Means are also provided for delivering the signature to an output lead in the form of a quotient bit, if desired.

Reliability of trench capacitors for VLSI memories : D. A. Baglee, C. Beydler, P. Shih and M. Yashiro. 24 a. Proc. IEEE Reliab. Phys. Symp., 215 (1986)

Reliability of trench capacitors for VLSI memories : D. A. Baglee, C. Beydler, P. Shih and M. Yashiro. 24 a. Proc. IEEE Reliab. Phys. Symp., 215 (1986)

On yield, fault distributions, and clustering of particles

Increasing the levels of semiconductor integration to larger chips with more transistors causes the fault and defect distributions of VLSI memory chips to deviate increasingly further from simple random Poisson statistics. The spatial distributions of particles on semiconductor wafers have been analyzed to gain insight into the nature of integrated circuit defect statistics. The analysis was done using grids of squares known as quadrats. It was found that the cluster parameter, which until now has been treated as a constant, did vary with quadrat area. The results also show that the deviation from Poisson statistics continues to increase into the realm of wafer-scale integration or WSI. Computer simulations were used to verify this effect.

IEE Review. Semiconductor memories

The paper reviews the evolution of semiconductor memories from the early 1960s to the present day. It includes descriptions and comparisons of the principal types of memory presently available, followed by a survey of the main semiconductor technologies used in the fabrication of VLSI memories. Typical cell designs are first presented, starting with basic electrical designs and proceeding to show how these may be implemented as layouts for a practical chip. The fabrication steps required to realise such cells within a memory chip are described. The design and organisation of complete memories is then discussed; the design of the principal types of read-only memories, read/write memories, content-addressable memories and serial memories being included. The remainder of the paper deals with the important topic of specification and timing requirements of memories; followed by a general review of different types of semiconductor memory, both from the applications point of view and as a comparison of their principal characteristics with those using alternative fabrication technologies. Finally, there is brief projection of future developments. The paper is written throughout primarily from the technological rather than the applications viewpoint.

Alpha-particle-induced charge collection measurements and the effectiveness of a novel p-well protection barrier on VLSI memories

This paper presents experimental results on analog charge collection measurements of alpha-particle-induced carriers in memory arrays. Measurements with high-intensity foils and variable-angle collimated sources on various memory arrays with different reflecting structures are reported. A novel p-well reflecting barrier is shown to reduce charge collection by a factor of 2 and soft error rate (SER) by about two orders of magnitude. Experimental analysis of the p-well with respect to its doping concentration, depth, bias voltage, and its interaction with p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-</sup> epi on p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> substrate are presented. The effectiveness of the p-well barrier is demonstrated on a 64k DRAM of 154 mils with extremely low SER ≤ 0.001 percent/1 kh at 1-µs cycle time.

A new VLSI memory cell using capacitance coupling (CC cell)

A new VLSI memory cell is proposed, which offers a small cell area, about 6F2(F is the feature size), readout signal gain, and high alpha-particle immunity. Since it employs capacitance coupling in a write operation, it requires only one bit line and is called a capacitance coupling (CC) cell. A CC cell consists of three transistors and a capacitor, which are integrated in a small area by sharing their nodes with one another. The charge is stored in a high-concentration p-type diffused layer (p+-layer) in a shallow n-type diffused layer (n-layer). The p+-layer potential controls the readout current which flows through the n-layer. To obtain both the p+-Iayer isolation and the large readout signal, trench isolation was employed. Experimental test devices having 0.7-µm deep n-layer, 0.2-µm deep p+-layer, and 1.5-µm deep trench isolation region were fabricated. They showed complete CC cell operation and 0/1 readout current ratio of more than 10.

A VLSI memory management chip: design considerations and experience

The design of a VLSI memory measurement chip which provides the WE 32001 microprocessor with an extensive set of memory management capabilities is described. The chip is implemented in 1.75 /spl mu/m twin-tub CMOS II technology and contains 92000 transistors. Highlights of the technology are the use of twin tubs for independently optimized n- and p-channel transistors, local oxidation and self-aligned channel-stops for parasitic field protection, and the use of an n/SUP +/ substrate for latchup protection. In addition, a composite layer of TaSi over n/SUP +/ polysilicon is used to achieve a fivefold reduction in sheet resistance over the conventional n/SUP +/ polysilicon. Electrical channel lengths for n-channel and p-channel transistors are nominally 1.5 /spl mu/m.

Soft error correction for increased densities in VLSI memories

If VLSI RAM densities are to continue to increase, it will undoubtedly be necessary to take the problems associated with much more seriously than has previously been done. In this paper, we propose a methodology for analyzing the effects of soft errors in VLSI RAMS as feature sizes decrease, and for taking corrective action with error-correcting codes. We will take a parametric approach, making several different assumptions about how the error severity will scale as feature size decreases, and our conclusions will be stated relative to the particular assumption made. It is our hope that as more definite information about VLSI error-scaling becomes available, the results of this paper will prove helpful for designers of ultra-dense memories.

Unidirectional error correction/detection for VLSI memory

Unidirectional error protecting codes for VLSI memories are described. After developing the theory of unidirectional error detection and correction, optimal systematic codes capable of detecting unidirectional errors are presented. Efficient single error correcting and d(d≥2)-unidirectional error detecting codes are also discussed.

Circuit techniques for a VLSI memory

This paper describes circuit techniques necessary for dynamic RAMs with high-packing density to implement submicron device technology. An on-chip error checking and correcting technique using bidirectional parity checking is proposed to reduce the soft error rate. In a sense-refresh amplifier, capacitor-coupled presenting is introduced to compensate for threshold imbalance. An on-chip supply voltage conversion is described as a solution for a hot carrier-injection problem. A 256K CMOS dynamic RAM has been designed and fabricated as a test vehicle for these techniques.

Laser Diffusion Connection Technology for VLSI Programming

A laser diffusion technology to connect poly-silicon conductors for programming VLSI memories is developed. It is based on the fact that a Nitrogen laser pumped dye laser of 510 nm wavelength irradiated on an intrinsic poly-silicon film in a VLSI, having 10 10 2 resistivity, decreases the film resistivity to 10 3 Ω. The mechanism of resistivity reduction is due to the laser heat diffusion of impurity into the intrinsic poly-silicon film. It is also clarified that the passivation film thick-ness on the intrinsic poly-silicon film changes laser reflectivity from zero to over 50%, affecting the condition of the process. The practical processing condition of laser diffusion connection for VLSI programming to enhance chip yield without damage is obtained.

Scaling of Gamma Dose Rate Upset Threshold in High Density Memories

Pulsed gamma upset threshold for high density RAMs is explored using constant field scaling rules. The analysis indicates that the upset threshold for DRAMs will not decrease with increased levels of integration and may improve relative to present technology. Potential improvement may be limited by statistical effects in gamma energy deposition. It is shown that statistical effects are magnified both by the increasing number of memory cells on a chip and by their extremely small feature size. Extreme value statistical techniques are used to determine worst-case cell memory loss. The paper also presents parallels of pulsed gamma and single event upset (SEU) effects that may be useful in SEU hardness assurance for VLSI memories.

A storage-node-boosted RAM with word-line delay compensation

A storage-node-boosted (SNB) RAM has been proposed and its advantages have been made clear for the VLSI memory. The new dynamic RAM architecture features the pulsed cell plates rather than the fixed potential cell plates, which stores 1.7 V/SUB DD/ for `H' in the cell without any boosted clocks and compensates the word-line delay. The 1 kbit test array has been fabricated with a 2 /spl mu/m level design rule. It provides a signal charge level of over 300 fC and a speed-up of 20 ns in a reading operation compared with the fixed cell plate potential cell.

Yield model for productivity optimisation of VLSI memory chips with redundancy and partially good product: C. H. Stapper, A. N. McLaren and M. Dreckmann IBM J. Res Develop. 24(3) 398 (1980)

Yield model for productivity optimisation of VLSI memory chips with redundancy and partially good product: C. H. Stapper, A. N. McLaren and M. Dreckmann IBM J. Res Develop. 24(3) 398 (1980)

Quadruply self-aligned stacked high-capacitance RAM using Ta2O5high-density VLSI dynamic memory

A new one-transistor, one-capacitor RAM cell structure called a Quadruply Self-Aligned Stacked High Capacitance (QSA SHC) RAM is proposed as a basic cell for a future one-million-bit VLSI memory. This cell consists of a QSA MOSFET and a Ta 2 O 5 capacitor stacked on it. By this cell, the ultimate cell area 3F \times 2F can be realized with sufficient operating margin. Here, F is the minimum feature size. The basic cell was fabricated and its operation was experimentally verified. The leakage current of Ta 2 O 5 film was small enough for the storage capacitor dielectric. Using a 3F \times 4F cell and a 4F pitch sense amplifier, a one-million-bit memory was designed with a 2-µm rule. A cell size of 6.5 × 8 µm2, and a chip size of 9.2 × 9.5 mm2were obtained. The access time, neglecting the RC time constant of the word line, was estimated to be about 170 ns. Based on this design, it is argued that a future one-million-bit memory can be realized by QSA SHC technology with a 2-1-µm process. The mask set of the 1-Mbit RAM was actually fabricated by an electron-beam mask maker. A photomicrograph of the 1-Mbit RAM chip patterned by the mask set is shown. This chip was patterned not to get an operating sample but to show an actual chip image of the future 1- Mbit RAM. The area of each circuit block including storage array can be seen in this chip image.