Virtex-5 Field Programmable Gate Array Research Articles

Optimized and robust implementation of mobile networks confidentiality and integrity functions

In mobile networks, sensitive information is transmitted over the radio link between the Base Station (BS) and the Mobile Station (MS). Therefore, a security mechanism based on confidentiality and integrity functions is designed to protect the anonymity of users’. More precisely, the confidentiality function was standardized by the Third Generation Partnership Project (3GPP) to protect users’ data and the integrity function to protect control (signaling) data. However, both functions are based on the same kernel algorithm. For example, the functions used in the Universal Mobile Telecommunications System (UMTS) network are based on the algorithm, namely the KASUMI block cipher. In this work, we proposed an optimized function that combines the confidentiality and integrity functions in one Running-Block-Cipher and ensures the same functionalities as the basic functions (UMTS F8 and F9 functions). We used an architectural synthesis technique that allows for achieving a significant reduction in the area occupied on the hardware device. The designed architecture was implemented on Xilinx Virtex Field Programmable Gate Arrays (FPGA) technology. The synthesis results after a place-and-route and comparison with previous works show the good performance of the proposed architecture in terms of throughput, consumed energy, and occupied hardware logic resources.

FPGA-Based Deep Convolutional Neural Network of Process Adaptive VMD Data With Online Sequential RVFLN for Power Quality Events Recognition

In this article, self-adaptive variational mode decomposition (SAVMD), deep convolutional neural networks (DCNN), and online-sequential random vector functional link networks (OSRVFLN) are integrated to categorize the single as well as combined power quality events (PQEs) in real time. The SAVMD method is proposed to optimize both the number of decomposition and data-fidelity factor to extract the most efficient band-limited mode (BLM) based on entropy and Kurtosis index. The most discriminative unsupervised features are extracted automatically using a DCNN from the BLM of SAVMD. The extracted distinct feature vector is fed to the proposed supervised OSRVFLN classifier to train accurately by minimizing the training cross-entropy loss with an increment in the number of hidden nodes for obtaining the maximum classification accuracy of the complex PQE patterns in noisy and noise-free environments. The automatic efficacious feature extraction, superior classification accuracy, noise immunity, and short event detection time are the major advantages of the proposed SAVMD-DCNN-OSRVFLN method. Finally, the novel methodology is implemented in a fast digital Xilinx Virtex-5 field-programmable gate array embedded processor to validate the practicability and feasibility of the proposed method in real-time.

Design and Implementation of High-Performance ECC Processor with Unified Point Addition on Twisted Edwards Curve

With the swift evolution of wireless technologies, the demand for the Internet of Things (IoT) security is rising immensely. Elliptic curve cryptography (ECC) provides an attractive solution to fulfill this demand. In recent years, Edwards curves have gained widespread acceptance in digital signatures and ECC due to their faster group operations and higher resistance against side-channel attacks (SCAs) than that of the Weierstrass form of elliptic curves. In this paper, we propose a high-speed, low-area, simple power analysis (SPA)-resistant field-programmable gate array (FPGA) implementation of ECC processor with unified point addition on a twisted Edwards curve, namely Edwards25519. Efficient hardware architectures for modular multiplication, modular inversion, unified point addition, and elliptic curve point multiplication (ECPM) are proposed. To reduce the computational complexity of ECPM, the ECPM scheme is designed in projective coordinates instead of affine coordinates. The proposed ECC processor performs 256-bit point multiplication over a prime field in 198,715 clock cycles and takes 1.9 ms with a throughput of 134.5 kbps, occupying only 6543 slices on Xilinx Virtex-7 FPGA platform. It supports high-speed public-key generation using fewer hardware resources without compromising the security level, which is a challenging requirement for IoT security.

FPGA implementation of an optimized A5/3 encryption algorithm

The radio link connecting users to network services is one of the most sensitive parts of mobile networks. This wireless channel is not protected physically to prevent unauthorized access to the carried information. Therefore, network providers use a security mechanism mainly based on cryptographic algorithms. For example, data protection (confidentiality) in the second and third generations of mobile networks is ensured using the A5/3 encryption algorithm (f8 function) standardized by the Third Generation Partnership Project (3GPP). In this work, we defined two main objectives for obtaining an optimized architecture of the A5/3 algorithm. The first one focuses on the optimization of the algorithm’s kernel (the KASUMI block cipher) by simplifying its internal architecture. The second one aims at the optimization of the A5/3 algorithm using a single block of the simplified KASUMI, unlike the standard A5/3 algorithm based on five blocks of the basic KASUMI. As a result, good performance has been achieved by considering the tradeoff between high throughput and required hardware logic resources compared to previous works. The proposed architecture was implemented on several Xilinx Virtex Field Programmable Gate Arrays (FPGA) technology devices. The synthesis results obtained after place and route have demonstrated the feasibility and efficiency of our solution. This promising technique can be applied to provide real-time data protection on embedded applications of mobile networks.

PUF-Based Secure Chaotic Random Number Generator Design Methodology

Pseudorandom number generators (PRNGs) play a pivotal role in generating key sequences of cryptographic protocols. Among different schemes, a simple chaotic PRNG (CPRNG) exhibits the property of being extremely sensitive to the initial seed and, hence, unpredictable. However, CPRNG is vulnerable if the initial seed is compromised. In this brief, we propose a novel physical unclonable function-based CPRNG (PUF-CPRNG), where the initial seed is secured by generating it from PUF. Furthermore, the proposed PUF-CPRNG includes dynamic refreshing logic to ensure that the random numbers generated are nonperiodic. To further secure the PUF-CPRNG, the feedback values of CPRNG are fed from PUF. An hardware architecture for the proposed methodology has been designed, and the proof of concept implementation was carried out using Xilinx Virtex-7 field-programmable gate array (FPGA). The proposed PUF-CPRNG passes the statistical test NIST 800-22, ENT, and correlation analysis.

Design and implementation of hydrogen economy using artificial neural network on field programmable gate array

In this study, economic analysis of the hydrogen generation and liquefaction system has been modeled using Multi-Layer Feed-Forward Artificial Neural Network (MLFFANN) and implemented on Field Programmable Gate Array (FPGA). Firstly, the 100X6 data set has been created to be used in the ANN-based modeling of the system using the Engineering Equation Solver (EES) program. This data set has been divided into two data sets as 80X6 for training and 20X6 for testing. The structure of the ANN-based economic analysis of hydrogen generation and liquefaction has been composed of 3 neurons in the input layer, ten neurons in the hidden layer, and three neurons in the output layer. Elliott-2-based TanSig transfer function and Purelin transfer function have been used in the neurons of the hidden layer and the output layer, respectively. Then, the ANN-model has been trained and tested using the Matlab program. The MSE values, 1.40x10E-7 and 2.07x10E-5, have been obtained as the results of the training phase and test phase of the ANN-based system, respectively. After getting fruitful results from training and testing phases, the economic analyses of hydrogen generation and liquation systems have been modeled in VHDL using bias and weight values located in the constructed ANN-based system using Matlab. The modeling has been performed in the Xilinx ISE Design Tools program using a 32-bit IEEE-754-1985 floating-point number standard. Then, the modeled ANN-based economic analysis of the hydrogen generation and liquation system has been implemented on the Xilinx Virtex-7 FPGA chip by performing the Place&Route process. The maximum operating frequency of the ANN-based hydrogen generation and liquefaction economy system implemented on FPGA has been obtained as 281.702 MHz using Xilinx ISE Design Tools.

A signed pulse-train-based image processor-array for parallel kernel convolution in vision sensors

PurposeThe purpose of this paper is to design a kernel convolution processor. High-speed image processing is a challenging task for real-time applications such as product quality control of manufacturing lines. Smart image sensors use an array of in-pixel processors to facilitate high-speed real-time image processing. These sensors are usually used to perform the initial low-level bulk image filtering and enhancement.Design/methodology/approachIn this paper, using pulse-width modulated signals and regular nearest neighbor interconnections, a convolution image processor is presented. The presented processor is not only capable of processing arbitrary size kernels but also the kernel coefficients can be any arbitrary positive or negative floating number.FindingsThe performance of the proposed architecture is evaluated on a Xilinx Virtex-7 field programmable gate array platform. The peak signal-to-noise ratio metric is used to measure the computation error for different images, filters and illuminations. Finally, the power consumption of the circuit in different operating conditions is presented.Originality/valueThe presented processor array can be used for high-speed kernel convolution image processing tasks including arbitrary size edge detection and sharpening functions, which require negative and fractional kernel values.

Requirement-driven model-based development methodology applied to the design of a real-time MEG data processing unit

The paper describes a multidisciplinary work that uses a model-based systems engineering method for developing real-time magnetoencephalography (MEG) signal processing. We introduce a requirement-driven, model-based development methodology (RDD and MBD) to provide a high-level environment and efficiently handle the complexity of computation and control systems. The proposed development methodology focuses on the use of System Modeling Language to define high-level model-based design descriptions for later implementation in heterogeneous hardware/software systems. The proposed approach was applied to the implementation of a real-time artifact rejection unit in MEG signal processing and demonstrated high efficiency in designing complex high-performance embedded systems. In MEG signal processing, biological artifacts in particular have a signal strength that overtop the signal of interest by orders of magnitude and must be removed from the measurement to achieve high-quality source reconstructions with minimal error contributions. However, many existing brain–computer interface studies overlook real-time artifact removal because of the demanding computational process. In this work, an automated real-time artifact rejection method is introduced, which is based on the recently presented method “ocular and cardiac artifact rejection for real-time analysis in MEG” (OCARTA). The method has been implemented using the RDD and MBD approach and successfully verified on a Virtex-6 field-programmable gate array.

Area and power‐efficient variable‐length fast Fourier transform for MR‐OFDM physical layer of IEEE 802.15.4‐g

The authors present a novel 16/32/64/128-point single-path delay feedback pipeline fast Fourier transform (FFT) architecture targeting the multi-rate and multi-regional orthogonal frequency division multiplexing (MR-OFDM) physical layer of IEEE 802.15.4-g. The proposed FFT architecture employs a mixed-radix algorithm to significantly reduce the number of complex multipliers. It utilises a configurable complex constant multiplier structure instead of a fixed constant multiplier to efficiently conduct W 32 , W 64 , and W 128 twiddle factor multiplication. A hardware-sharing mechanism has also been formulated to reduce the memory space requirements of the proposed 16/32/64/128-point FFT computation scheme. The proposed design is implemented in Xilinx Virtex-5 and Altera's field-programmable gate array devices. For the computation of 128-point FFT, the proposed mixed-radix FFT architecture significantly reduces the hardware cost in comparison with existing FFT architecture. The proposed FFT architecture is also implemented by adopting the 90 nm complementary metal-oxide-semiconductor technology with a supply voltage of 1 V. Post-synthesis results reveal that the design is efficient in terms of gate count and power consumption, compared to earlier reported designs. The proposed variable-length FFT architecture gate count is 22.3K and consumes 3.832 mW, while the word-length is 12-bits and can be efficiently useful for the IEEE 802.15.4-g standard.

Dual-Mode FPGA-Based Triple-TDC With Real-Time Calibration and a Triple Modular Redundancy Scheme

This paper proposes a triple time-to-digital converter (TDC) for a field-programmable gate array (FPGA) platform with dual operation modes. First, the proposed triple-TDC employs the real-time calibration circuit followed by the traditional tapped delay line architecture to improve the environmental effect for the application of multiple TDCs. Second, the triple modular redundancy scheme is used to deal with the uncertainty in the FPGA device for improving the linearity for the application of a single TDC. The proposed triple-TDC is implemented in a Xilinx Virtex-5 FPGA platform and has a time resolution of 40 ps root mean square for multi-mode operation. Moreover, the ranges of differential nonlinearity and integral nonlinearity can be improved by 56 % and 37 % , respectively, for single-mode operation.

Area-Time Efficient Hardware Implementation of Modular Multiplication for Elliptic Curve Cryptography

In this paper, an area-time efficient hardware implementation of modular multiplication over five National Institute of Standard and Technology (NIST)-recommended prime fields is proposed for lightweight elliptic curve cryptography (ECC). A modified radix-2 interleaved algorithm is proposed to reduce the time complexity of conventional interleaved modular multiplication. The proposed multiplication algorithm is designed in hardware and separately implemented on Xilinx Virtex-7, Virtex-6, Virtex-5, and Virtex-4 field-programmable gate array (FPGA) platforms. On the Virtex-7 FPGA, the proposed design occupies only 1151, 1409, 1491, 2355, and 2496 look up tables (LUTs) and performs single modular multiplication in 0.93 μs, 1.18 μs, 1.45 μs, 2.80 μs, and 4.69 μs with maximum clock frequencies of 207.1 MHz, 190.7 MHz, 177.3 MHz, 137.6 MHz, and 111.2 MHz over five NIST prime fields of size 192, 224, 256, 384, and 521 bits, respectively. The hardware implementations on the Virtex-6, Virtex-5, and Virtex-4 FPGAs also show that the proposed design is highly efficient in terms of hardware resource utilization and area-delay product compared with other designs for modular multiplication.

Algorithm and VLSI Design for 1-Bit Data Detection in Massive MIMO-OFDM

The use of low-resolution data converters in the radio-frequency (RF) chains of all-digital massive multiple-input multiple-output (MIMO) basestations promises significant reductions in power consumption, hardware costs, and interconnect bandwidth. We propose a quantization-aware data-detection algorithm which mitigates the performance loss of 1-bit quantized massive MIMO orthogonal frequency-division multiplexing (OFDM) systems. Since the system performance heavily depends on the quality of channel estimates, we also develop a nonlinear 1-bit channel estimation algorithm that builds upon the proposed data detection algorithm. We show that the proposed algorithms significantly outperform linear data detectors and channel estimators in terms of bit error rate. For the proposed nonlinear data detection algorithm, we develop a very large scale integration (VLSI) architecture and present implementation results on a Xilinx Virtex-7 field programmable gate array (FPGA). Our implementation results are, to the best of our knowledge, the first for 1-bit massive MU-MIMO-OFDM systems and demonstrate comparable hardware efficiency with respect to state-of-the-art linear data detectors designed for systems with high-resolution data converters, while achieving lower bit error rate.

An In-Sight Into How Compression Dictionary Architecture Can Affect the Overall Performance in FPGAs

This paper presents a detailed analysis of various approaches to hardware implemented compression algorithm dictionaries, including our optimized method. To obtain comprehensive and detailed results, we introduced a method for the fair comparison of programmable hardware architectures to show the benefits of our approach from the perspective of logic resources, frequency, and latency. We compared two generally used methods with our optimized method, which was found to be more suitable for maintaining the memory content via (in)valid bits in any mid-density memory structures, which are implemented in programmable hardware such as FPGAs (Field Programmable Gate Array). The benefits of our new method based on a “Distributed Memory” technique are shown on a particular example of compression dictionary but the method is also suitable for another use cases requiring a fast (re-)initialization of the used memory structures before each run of an algorithm with minimum time and logic resources consumption. The performance evaluation of the respective approaches has been made in Xilinx ISE and Xilinx Vivado toolkits for the Virtex-7 FPGA family. However the proposed approach is compatible with 99% of modern FPGAs.

A Novel Parallel Approach for Disjoint Rule Generation and Optimization (DRGO) in Reconfigurable Firewall Using FPGA

The packet classification is a core function of firewall, which is widely used in various applications of network infrastructure for security purpose. Nowadays, speed of data transfer is in Gbps. So, processing the packet at the same speed is very challenging task to achieve high throughput. In this paper, a field-programmable gate array (FPGA)-based reconfigurable firewall, namely DRGO firewall, is proposed that accepts only unique rule and processes packet in parallel. DRGO firewall resolves rule ambiguity in the rule set to perform deterministic action for an incoming packet and minimizes cardinality of ruleset to achieve better space efficiency and higher throughput. Such type of firewall is applicable in any network to classify unknown incoming packets. The storage cost per rule of DRGO firewall is 14 bytes. The proposed approach is implemented on Virtex-6 FPGA, and it achieves throughput of 142 Gbps at the clock rate of 442.6 MHz for minimum packet size of 40 bytes.

High Speed Partial Pattern Classification System Using a CAM-Based LBP Histogram on FPGA

This letter proposes a novel partial pattern classification system that uses local binary patterns as a classifier and a content-addressable memory, which has the parallel search capability, to perform classification at a higher speed. The proposed pattern classification system uses Manhattan distance for class assignment and further uses logical resources on the Xilinx Virtex-7 field-programmable gate array to perform classification. Our proposed system assigns a class to a pattern of any size and shape in as less as $1.12~\mu \text{s}$ , which is 33% faster than the state-of-the-art pattern classification system.

Design of an Area-Efficient Various N-point Support radix-2/22 FFT using Modified Butterfly Units

Fast Fourier Transform (FFT) acts as an element in the high-speed signal processing application, which involves the following subsequent operations, namely complex addition, complex subtraction and complex multiplication. Due to the complex multiplication operation, the FFT structures lead to more hardware demand. Hence, this work introduces an area-efficient various N-point support radix-2 and radix-22 FFT structure by using proposed modified butterfly units and radix-2/22 butterfly unit. The proposed modified butterfly units are used to reduce the number of complex multipliers effectively. For this reason, it is using for certain conditions in FFT design instead of existing radix-2/22 butterfly unit. Further, the proposed design supported to perform various size of FFT in a single architecture without increasing the extra element demand. Moreover, the proposed FFT structure designed and implemented using a Xilinx Virtex-6 Field-Programmable Gate Array (FPGA) device (6vcx75tff484-2) and Cadence tool with 45nm CMOS technology. The implementation results demonstrate that the proposed N-point (N=16, 32 and 64) DIF-FFT design attains the less hardware complexity when compared with existing multi-mode FFT design. Then the proposed area-efficient 16-point, 32-point and 64-point radix-2 FFT architectures reduce the total area by 20.99%, 11% and 4.9% respectively. As well, the proposed area-efficient 16-point, 32-point and 64-point radix-22 FFT architectures reduce the total area by 32%, 19% and 11% respectively.

Incremental Gaussian Elimination Approach to Implement OMP for Sparse Signal Measurement

An efficient architecture of the orthogonal matching pursuit (OMP) algorithm is proposed to recover signals compressively measured at the sub-Nyquist rate. The proposed architecture is implemented on the field-programmable gate array (FPGA) for performance validation. In the place of matrix factorization-based pseudoinverse computation, Gaussian elimination (GE) is used to compute the signal estimate. A novel incremental Gaussian elimination (IGE) algorithm is proposed and used in the OMP algorithm. The proposed design is targeted to the Virtex6 FPGA device to compare with other reported works for $K=256$ , $N=1024$ , and $m=36$ , where $N$ is the number of samples, $K$ is the measurement vector length, and $m$ is the signal sparsity level. The recovery signal-to-noise ratio (RSNR) of 23.98 dB is achieved. The proposed work is validated by implementing it on the Artix7 FPGA device by taking compressed measurements from an analog to information converter (AIC). The input signal is synthesized as a random combination of sine waves with different frequencies. The proposed architecture is hardware-efficient and faster, and consumes low dynamic power than other existing designs. The proposed design is hardware-efficient even for the higher value of $m/K$ .

FPGA Implementation of Weighted Online Sequential Extreme Learning Machine for Data Classification

To design an efficient embedded module field-programmable gate array (FPGA) plays significant role. FPGA, a high speed reconfigurable hardware platform has been used in various field of research to produce the throughput efficiently. A now-a-days artificial neural network (ANN) is the most prevalent classifier for many analytical applications. In this paper, weighted online sequential extreme learning machine (WOS-ELM) classifier is presented and implemented in hardware environment to classify the different real-world bench-mark datasets. The faster learning speed, remarkable classification accuracy, lesser hardware resources, and short-event detection time, aid the hardware implementation of WOS-ELM classifier to design an embedded module. Finally, the developed hardware architecture of the WOS-ELM classifier is implemented on a high speed reconfigurable Xilinx Virtex (ML506) FPGA board to demonstrate the feasibility, effectiveness, and robustness of WOS-ELM classifier to classify the data in real-time environment.

A Low-Error, Memory-Based Fast Binary Logarithmic Converter

This brief presents a memory based fast binary logarithmic converter based on a piecewise linear approximation technique. The proposed method is simple and arithmetic operation-less, which achieves 10−4 to 10−3 maximum absolute error (MAE) while maintaining a high speed. The approach partitions the logarithmic curve of the fractional component into $2^{L}$ uniform regions and a block RAM (size $2^{L} \times $ bits) stores the approximate value of each sub-region. For any number, most significant $L$ bits of the fractional component address the memory location of the logarithmic converter. The hardware synthesis result, implemented with 26 bits fractional precision on Virtex-6 field-programmable gate array device, shows 75% improvement in MAE and 27% decrease in critical path delay compared to the current state-of-the-art techniques in the worst-case scenario. In Otsu’s image thresholding algorithm, the proposed logarithmic converter with 3.08 ( $=2^{8} \times 12$ ) kbits memory size adequately meets the accuracy requirement for improved image segmentation.

High throughput implementation of SHA3 hash algorithm on field programmable gate array (FPGA)

Cryptographic hash function is an essential element in sensitive communications, such as banking, military and health. It ensures secure communication by checking data integrity, storing passwords and other important roles. Keccak hash function (i.e. SHA3) is the best one in terms of resistance against recent cryptanalysis attacks as well as of hardware performance. However, an efficient improvement in terms of hardware performance is always needed, such as increasing speed or decreasing area consumption. In this paper, we have focused on improving the speed (throughput) of Keccak hash algorithm by proposing a new design which is based on decreasing the number of clock cycles needed to produce a hash value. Consequently, we could achieve 33.35 Gbps as a highest achieved throughput. However, a decrease in terms of maximum frequency has been noticed. Our design has been implemented in Xilinx Virtex5 and Virtex6 FPGA device, and has been compared to recent published implementations.