FPGA implementation of an optimized A5/3 encryption algorithm

Abstract

The radio link connecting users to network services is one of the most sensitive parts of mobile networks. This wireless channel is not protected physically to prevent unauthorized access to the carried information. Therefore, network providers use a security mechanism mainly based on cryptographic algorithms. For example, data protection (confidentiality) in the second and third generations of mobile networks is ensured using the A5/3 encryption algorithm (f8 function) standardized by the Third Generation Partnership Project (3GPP). In this work, we defined two main objectives for obtaining an optimized architecture of the A5/3 algorithm. The first one focuses on the optimization of the algorithm’s kernel (the KASUMI block cipher) by simplifying its internal architecture. The second one aims at the optimization of the A5/3 algorithm using a single block of the simplified KASUMI, unlike the standard A5/3 algorithm based on five blocks of the basic KASUMI. As a result, good performance has been achieved by considering the tradeoff between high throughput and required hardware logic resources compared to previous works. The proposed architecture was implemented on several Xilinx Virtex Field Programmable Gate Arrays (FPGA) technology devices. The synthesis results obtained after place and route have demonstrated the feasibility and efficiency of our solution. This promising technique can be applied to provide real-time data protection on embedded applications of mobile networks.