Vertical Junction Field Effect Transistor Research Articles

Study of drain induced channel effects in vertical GaN junction field-effect transistors

Study of drain induced channel effects in vertical GaN junction field-effect transistors

Simulation And Design of a Vertical Gallium Nitride JFET with Dual Lateral Heterojunction Channels

A novel vertical gallium nitride (GaN) junction field-effect transistor (JFET) is reported in this article. Through the setup of dual lateral heterojunction channels in the body, the current density is high while the p-type gallium nitride growth area can be adjusted to easily achieve enhanced mode. Based on the structure parameter settings in this article, through the device simulation software TCAD, and under the condition of selecting the appropriate p-type GaN growth region, the threshold voltage of the device is 1.1 V, the source output current density can reach 7.2 kA/cm2, the breakdown voltage is about 750 V, and the on-resistance is 0.52 mΩ·cm2. Finally, the test circuit is built, and the switching characteristics of the device proposed in this paper are simulated under the consideration of parasitic inductance.

Impact of Dimensions and Doping on the Breakdown Voltage of a Trench 4H-SiC Vertical JFET

In this paper we study the feasibility of the design/fabrication of a vertical trench 4H-SiC Junction Field Effect Transistor (JFET), assuming realistic constraints of the depth of the P+ implantation. The P+ doping profile is obtained using a Monte Carlo implantation simulation. The calculation used a drift-diffusion approach. The JFET aims to achieve a threshold voltage of-3V. We found that this constraint in concomitance with the proposed structure limits the breakdown voltage to approximately 200V. This is the result of a premature breakdown induced by short channel effects, namely Drain Induced Barrier Lowering (DIBL). However, a negative increase in the gate bias represses this short channel effect and improves the breakdown voltage to roughly 1800V. At this gate bias, the breakdown is induced by reaching the critical field strength of 4H-SiC at the gate P+/N junction, which causes avalanche generation of carriers. In addition, we have calculated the dependence of the threshold voltage on the drift doping and pillar width. This work also shows the vulnerability of the design to random fluctuation in the doping profile.

Temperature Dependent Analytical Model for the Threshold Voltage of the SiC VJFET with a Lateral Asymmetric Channel

The wide-bandgap (WBG) semiconductor devices for modern power electronics require intensive efforts for the analysis of the critical aspects of their operation. In recent years, silicon carbide (SiC) based field effect transistor have been extensively investigated. Motivated by the significant employment of the SiC Vertical Junction Field Effect transistors with lateral channel (LC-VJFET) in the development of high-voltage and high temperature applications, the properties of the LC-VJFET device are investigated in this work. The most important normally-ON LC-VJFET parameter is their threshold voltage (VTh), which is defined as the gate-to-source voltage necessary to block the device. The higher complexity of the blocking operation of the normally-ON device makes the accurate knowledge of the VTh as a fundamental issue. In this paper, a temperature dependent analytical model for the threshold voltage of the normally-ON LC-VJFET is developed. This analytical model is derived based on a numerical analysis of the electrical potential distribution along the asymmetrical lateral channel in the blocking operation. To validate our model, the analytical results are compared to 2D numerical simulations and experimental results for a wide temperature range.

A novel GaN vertical junction field-effect transistor with intrinsic reverse conduction capability and kilo-volt breakdown voltage

In this work, a novel GaN vertical junction field-effect transistor (JFET) with intrinsic reverse conduction capability (RC-JFET) is proposed and studied by simulation. The RC-JFET features two separate source electrodes, one of which performs as an embedded freewheeling diode that can enable the reverse conduction function of the device. Benefiting from a structure with two separate source electrodes, the forward and reverse current conduction paths are also separated, which allows us to independently design the forward and reverse conduction characteristics of the RC-JFET. The forward threshold voltage V TH is 1.6 V while the reverse turn-on voltage V on,rev is as low as 0.7 V. In addition, the buried floating p-base can effectively modulate the E-field in the GaN drift region, which can achieve a high breakdown voltage of 1720 V with an R on,sp of 2.79 mΩ cm2. Due to the embedded freewheeling diode, the device exhibits a short reverse recovery time T rr of 13 ns. By featuring an intrinsic reverse conduction capability, the proposed RC-JFET is capable of eliminating the externally connected diode, which is beneficial for improved switching speed and switching power loss due to the reduction of parasitic effects and chip size of power circuits.

A Normally-off Copackaged SiC-JFET/GaN-HEMT Cascode Device for High-Voltage and High-Frequency Applications

A 1200-V/100-mΩ silicon carbide (SiC) junction field-effect-transistor (JFET)/ gallium nitride (GaN) high-electron-mobility-transistor (HEMT) hybrid power switch is demonstrated, which features a flip-chip copackaged cascode configuration incorporating a vertical SiC JFET and a lateral GaN-HEMT. The high-voltage SiC-JFET provides the high-voltage blocking capability while the low-voltage GaN-HEMT enables the normally- off gate control with superior switching characteristics. Compared to conventional SiC-JFET/Si- mosfet cascode devices, the SiC-JFET/GaN-HEMT cascode device exhibits fast switching speed, which has been validated by systematic characterizations including static/dynamic device-level measurements and board-level hard-switching tests. Meanwhile, the device is free from several notorious issues of high-voltage GaN power transistors such as dynamic on -state resistance degradation and threshold voltage shift. Such a wide-bandgap semiconductor-based hybrid switch is suitable to be deployed in high-power and high-efficiency power conversion systems.

Performance evaluation of normally ON/OFF junctionless vertical channel GaN FET

GaN vertical channel junction field-effect transistor (VC-JFET) is a relatively new technology, which is particularly suitable for high-power applications. In these devices, the channel is formed between two p-GaN current blocking layers which is a complex and costly process. In addition, various traps and defects get introduced during the fabrication of p-GaN layers. The traps and defects near the interface of the p-GaN layer and n-GaN channel can deteriorate the device performance. Therefore, for reducing the fabrication complexity with enhanced device performance, a normally ON/OFF GaN vertical channel junctionless field-effect transistor (VC-JLFET) is proposed in this paper. The results are compared against conventional GaN VC-junction field-effect transistor (VC-JFET) of the equal dimensions and doping concentrations. The absence of p–n junction at source and drain in the proposed device offers less fabrication complexity, cost, and thermal budget as compared to the referenced device. The proposed device provides more than four times drain current ( $$8.37\times 10^{-6}$$ A/μm) as compared to the referenced device ( $$1.9 \times 10^{-6}$$ A/μm) at similar physical and bias conditions. The obtained values of ON resistance, trans-conductance, unity gain bandwidth frequency, and breakdown voltage for the proposed normally ON device (at Lap = 0.9 μm, Vth = −3.5 V, VG = −1V, VD = 1 V) are 5.63 × 103 Ω/μm, 6.99 × 10−7 S/μm, 1.56 × 108 Hz and 700 V, respectively. While in normally OFF mode, the obtained values of parameters such as threshold voltage, ON resistance, breakdown voltage, and drain current are 2 V, $$1.56 \times 10^{6}$$ Ω/μm, greater than 1000 V and $$1.54 \times 10^{-6}$$ A/μm, respectively. The normally OFF VC-JLFET is achieved by gate work-function engineering in conjunction with doping optimization.

Cross-Section Doping Topography of 4H-SiC VJFETs by Various Techniques

Different methods for cross-section characterization of SiC Trenched-singly-implanted vertical junction field effect transistors (TSI-VJFETs) are presented with the purpose to determine the epitaxial structure in terms of doping topography.

A New Vertical JFET Power Device for Harsh Radiation Environments

An increasing demand for power electronic devices able to be operative in harsh radiation environments is now taking place. Specifically, in High Energy Physics experiments the required power devices are expected to withstand very high radiation levels which are normally too hard for most of the available commercial solutions. In this context, a new vertical junction field effect transistor (JFET) has been designed and fabricated at the Instituto de Microelectrónica de Barcelona, Centro Nacional de Microelectrónica (IMB-CNM, CSIC). The new silicon V-JFET devices draw upon a deep-trenched technology to achieve volume conduction and low switch-off voltage, together with a moderately high voltage capability. The first batches of V-JFET prototypes have been already fabricated at the IMB-CNM clean room, and several aspects of their design, fabrication and the outcome of their characterization are summarized and discussed in this paper. Radiation hardness of the fabricated transistors have been tested both with gamma and neutron irradiations, and the results are also included in the contribution.

Channel width effect on the operation of 4H-SiC vertical JFETs

SiC JFETs may have the lowest overall losses of switching devices and can operate at temperatures over 400 °C. Over different junction field-effect transistor (JFET) designs, the trenched and implanted (TI) gate vertical JFET (TI-VJFET) is very attractive since it may have the lowest on-resistance and its fabrication does not require epitaxial overgrowth or multiple angled implantation. 4H-SiC TI-VJFETs have been fabricated with self-aligned nickel silicide source and gate contacts using a process sequence that greatly reduces process complexity as it includes only four lithography steps. Different design factors, including channel width, channel length, and mesa height, are considered. The effect of the channel geometry on the electrical characteristics has been studied by varying their width (1.5–5 µm). The specific ON resistance (RON) of the fabricated devices, at VGS = 0 V, varied from 12.5 to 6.2 mΩ cm2 with increasing the channel width. The effect of the channel width was more tremendous on the breakdown voltage of the transistors passing from 80 to 500 V, showing the importance of the static-induction effect (saddle point potential influenced by drain potential) on the transistor blocking characteristics. Indeed, the blocking voltage gain is varying from 50 to single digit values when increasing the channel width. The physical reason is that the blocking gain to first order depends exponentially on the channel dimensions as the drain-source current is exponentially related to the saddle point potential.

Characterization of vertical GaN p–n diodes and junction field-effect transistors on bulk GaN down to cryogenic temperatures

There is great interest in wide-bandgap semiconductor devices and most recently in vertical GaN structures for power electronic applications such as power supplies, solar inverters and motor drives. In this paper the temperature-dependent electrical behavior of vertical GaN p–n diodes and vertical junction field-effect transistors fabricated on bulk GaN substrates of low defect density (104 to 106 cm−2) is described. Homoepitaxial MOCVD growth of GaN on its native substrate and the ability to control the doping in the drift layers in GaN have allowed the realization of vertical device architectures with drift layer thicknesses of 6 to 40 μm and net carrier electron concentrations as low as 1 × 1015 cm−3. This parameter range is suitable for applications requiring breakdown voltages of 1.2 kV to 5 kV. Mg, which is used as a p-type dopant in GaN, is a relatively deep acceptor (EA ≈ 0.18 eV) and susceptible to freeze-out at temperatures below 200 K. The loss of holes in p-GaN has a deleterious effect on p–n junction behavior, p-GaN contacts and channel control in junction field-effect transistors at temperatures below 200 K. Impact ionization-based avalanche breakdown (BV > 1200 V) in GaN p–n junctions is characterized between 77 K and 423 K for the first time. At higher temperatures the p–n junction breakdown voltage improves due to increased phonon scattering. A positive temperature coefficient in the breakdown voltage is demonstrated down to 77 K; however, the device breakdown characteristics are not as abrupt at temperatures below 200 K. On the other hand, contact resistance to p-GaN is reduced dramatically above room temperature, improving the overall device performance in GaN p–n diodes in all cases except where the n-type drift region resistance dominates the total forward resistance. In this case, the electron mobility can be deconvolved and is found to decrease with T−3/2, consistent with a phonon scattering model. Also, normally-on vertical junction field-effect transistors with BV = 1000 V and drain currents of 4 A are fabricated and characterized over the same temperature range. It is demonstrated that vertical GaN devices (diodes and transistors) utilizing p–n junctions are suitable for most practical applications including automotive ones (210 K < T < 423 K). While devices are functional at cryogenic temperatures (77 K) there may be some limitations to their performance due the freeze-out of Mg acceptors.

Reliability studies of vertical GaN devices based on bulk GaN substrates

There is great interest in wide band-gap semiconductor devices and most recently in vertical GaN structures for power electronic applications. In this paper initial reliability studies of vertical p–n diodes and vertical junction field effect transistors fabricated on pseudo bulk low defect density (104 to 106cm−2) GaN substrates are discussed. Homoepitaxial MOCVD growth of GaN on its native substrate and being able to control the doping in the drift layers in GaN has allowed the realization of vertical device architectures with drift layer thicknesses of 6 to 40μm and net carrier electron concentrations of 2×1015 to 2×1016cm−3. This parameter range is suitable for applications requiring breakdown voltages of 1200V to 5kV with a proper edge termination strategy. Measured devices demonstrate power device figure of merit of differential specific on-resistance (Rsp) of 2.8mΩ-cm2 for a breakdown voltage of 4.1kV. The improvement in the substrate quality over the last few years has resulted in the fabrication of diodes with areas as large as 16mm2, with breakdown voltages exceeding 1200V, and pulsed (100μs) currents of 100–400A. Furthermore, impact ionization based avalanche breakdown has been demonstrated in GaN for the first time due to the high quality of the crystals grown on the native substrates. With these key demonstrations firmly in place, it is necessary to evaluate the reliability performance of vertical GaN devices on bulk GaN substrates. The results of high temperature reverse bias (HTRB), high temperature operating life (HTOL), temperature humidity bias (THB), temperature cycling (TC), and inductive avalanche ruggedness tests conducted on vertical GaN devices packaged in standard power packages are reported. It is observed that fundamental failure mechanisms are almost always traced back to the starting substrate material quality, substrate miscut angle, and surface morphology post epi growth. No observation of Rds drift is made for vertical diodes or transistors fabricated on bulk GaN substrates under the stress conditions mentioned above once a suitable back metal and die attach process is developed.

Static and switching characteristics of 3.3 kV double channel-doped SiC vertical junction field effect transistor in cascode configuration

A silicon-carbide (SiC) junction field-effect transistor (JFET)/Si metal–oxide–semiconductor field-effect transistor (MOSFET) cascode is a good solution owing to its high reliability, low on-resistance, high switching speed, and good gate controllability. A 3.3 kV SiC vertical JFET using a double channel doping technique is proposed in this paper. The characteristics of a cascode including the developed JFET are also presented. A blocking voltage higher than 4.0 kV and a low on-resistance of 14.7 mΩ cm2 were realized. The saturation current of the cascode was suppressed by controlling the threshold voltage of the JFET. Moreover, small switching losses were obtained.

A model of the off-behaviour of 4H–SiC power JFETs

A physical model of the off-behaviour of Vertical Junction Field Effect Transistors (VJFETs) up to their blocking voltage limit is presented. Since the drain current, ID, of these devices strongly depends on the amount of the voltage barrier occurring in the channel, the model is capable to describe the drain voltage dependence of the voltage barrier and of ID from VDS=0V up to maximum VDS value (kV) sustained from device and to describe the effects of geometry and doping of channel. The accuracy of the model is proven by comparing the ID–VDS curves with numerical simulations of devices designed with different gate depth, channel width, and epilayer thickness. The agreement between model, numerical simulations and literature data confirms the capability of model to describe the ID–VDS curves of devices having a pentode or triode like behaviour.

Normally-on 4H-SiC Vertical Junction Field Effect Transistor (VJFET): Design and Analysis Using TCAD Simulation

This paper reports on the results of simulations of normally-on 4H-SiC VJFET for high voltage applications. We use Sentaurus TCAD simulator to investigate the breakdown voltage with channel widths of 0.6 and 0.9μm under limited negative gate bias. It is observed that high negative gate voltage is needed more likely for wider channel opening. Simulation results show that breakdown voltage decreases with increasing negative gate voltage. In addition, the effect of drift doping on breakdown voltage is discussed. The maximum breakdown voltage of approximately 11kV is achieved with drain leakage current of the order of 10-7 A. The novelty of proposed design verifies the improvement in breakdown voltage observed by the experimentally reported data.

Switching Performance of Normally-off 4H-SiC TI-VJFET

Vertical-Junction-Field-Effect-Transistors (VJFETs) are currently the most mature 4H-SiC devices for high power/temperature and switching application. In this paper, switching characteristics of TI-VJFETs have been studied using 2D Sentaurus TCAD with variation of gate-drain capacitance (1∼50 pF) and temperature (RT∼200°C). It was found that switching time and energy losses increase with increase in gate–drain capacitance while as temperature increase from 25°C to 200°C, turn-on and energy loss (3∼ 5ns & 1.8∼3μJ) increase while turn-off and energy loss (9∼6ns & 5.4 ∼3.6μJ) decrease.

Fabrication and Characterisation of 1200V 4H-SiC VJFET

Results are presented for the silicon carbide (SiC) vertical channel junction field effect transistor (VJFET) fabricated based on in-house SiC epitaxial wafer suitable for power devices. We have demonstrated continuous improvement in blocking voltage, forward drain current under high temperature. The SiC VJFET device’s current density is 360 A/cm2 and current is 11 A at VG= 3 V and VD = 2 V, with related specific on-resistance 5.5 mΩ·cm2. The device exceeds 1200 V at gate bias VG = -10V. The current of the SiC VJFET device is 4 A and the reverse voltage is 1200V at the 200 °C high temperature.

Design consideration and fabrication of 1.2-kV 4H-SiC trenched-and-implanted vertical junction field-effect transistors

We present the design consideration and fabrication of 4H-SiC trenched-and-implanted vertical junction field-effect transistors (TI-VJFETs). Different design factors, including channel width, channel doping, and mesa height, are considered and evaluated by numerical simulations. Based on the simulation result, normally-on and normally-off devices are fabricated. The fabricated device has a 12 μm thick drift layer with 8×1015 cm−3 N-type doping and 2.6 μm channel length. The normally-on device shows a 1.2 kV blocking capability with a minimum on-state resistance of 2.33 mΩ·cm2, while the normally-off device shows an on-state resistance of 3.85 mΩ·cm2. Both the on-state and the blocking performances of the device are close to the state-of-the-art values in this voltage range.

Design and Performances of 4H-SiC Bipolar Mode Field Effect Transistor (BMFETs)

An original design of 4H polytype of silicon carbide (4H-SiC) bipolar-mode field-effect transistors (BMFETs), which combines the on-state operation of silicon version with the off-state behavior of SiC-VJFETs (vertical junction field-effect transistor), is analyzed by numerical simulations. Using the physical parameters extracted from the previous experimental analysis, this paper shows the feasibility of 4H-SiC BMFETs to manage drain current densities as high as 500 A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> with a current gain of 50 and to sustain blocking voltage of 2.1 kV. Comparisons with the existing 4H-SiC power transistors, like bipolar junction transistors (BJTs), VJFETs, and double-diffusive metal-oxide-semiconductor FETs, show that, besides a thermal stability in the examined range 300-523 K, BMFET exhibits the low on-resistance of BJTs and can operate at the high frequencies of power FETs.

Analysis and Experimental Verification of the Influence of Fabrication Process Tolerances and Circuit Parasitics on Transient Current Sharing of Parallel-Connected SiC JFETs

Operation of parallel-connected 4H-SiC vertical junction field effect transistors (VJFETs) from SemiSouth is modeled using numerical simulations and experimentally verified. The unbalanced current waveforms of parallel-connected VJFETs are investigated with respect to the spread in the critical parameters of the device structure and to the influence of the parasitic inductances in the measurement circuit. The device structures are reconstructed based on scanning electron microscopy (SEM) analysis, electrical characterization, and device simulations. The doping concentration and profile depth of a p-grid formed by angular implantation are studied as main contributors that influence the variation of the on-state characteristics, and the threshold voltage of the experimental devices. It has been shown elsewhere that similar differences in p-grid also lead to differences in gate-source breakdown voltage. The switching performance of the parallel-connected JFETs is measured using single and double gate drivers in a double-pulse test and compared with simulations. The switched current and voltage waveforms from measurements are reproduced in simulation by introducing the parasitics. From the analysis, it is found that reasonable differences in doping levels and profiles of the p-grid give rise to significant differences in device parameters. However, even with these parameter differences and circuit asymmetries, it is possible to successfully operate parallel-connected VJFETs of this type.