Performance evaluation of normally ON/OFF junctionless vertical channel GaN FET

Abstract

GaN vertical channel junction field-effect transistor (VC-JFET) is a relatively new technology, which is particularly suitable for high-power applications. In these devices, the channel is formed between two p-GaN current blocking layers which is a complex and costly process. In addition, various traps and defects get introduced during the fabrication of p-GaN layers. The traps and defects near the interface of the p-GaN layer and n-GaN channel can deteriorate the device performance. Therefore, for reducing the fabrication complexity with enhanced device performance, a normally ON/OFF GaN vertical channel junctionless field-effect transistor (VC-JLFET) is proposed in this paper. The results are compared against conventional GaN VC-junction field-effect transistor (VC-JFET) of the equal dimensions and doping concentrations. The absence of p–n junction at source and drain in the proposed device offers less fabrication complexity, cost, and thermal budget as compared to the referenced device. The proposed device provides more than four times drain current ( $$8.37\times 10^{-6}$$ A/μm) as compared to the referenced device ( $$1.9 \times 10^{-6}$$ A/μm) at similar physical and bias conditions. The obtained values of ON resistance, trans-conductance, unity gain bandwidth frequency, and breakdown voltage for the proposed normally ON device (at Lap = 0.9 μm, Vth = −3.5 V, VG = −1V, VD = 1 V) are 5.63 × 103 Ω/μm, 6.99 × 10−7 S/μm, 1.56 × 108 Hz and 700 V, respectively. While in normally OFF mode, the obtained values of parameters such as threshold voltage, ON resistance, breakdown voltage, and drain current are 2 V, $$1.56 \times 10^{6}$$ Ω/μm, greater than 1000 V and $$1.54 \times 10^{-6}$$ A/μm, respectively. The normally OFF VC-JLFET is achieved by gate work-function engineering in conjunction with doping optimization.