Normally-on 4H-SiC Vertical Junction Field Effect Transistor (VJFET): Design and Analysis Using TCAD Simulation

Abstract

This paper reports on the results of simulations of normally-on 4H-SiC VJFET for high voltage applications. We use Sentaurus TCAD simulator to investigate the breakdown voltage with channel widths of 0.6 and 0.9μm under limited negative gate bias. It is observed that high negative gate voltage is needed more likely for wider channel opening. Simulation results show that breakdown voltage decreases with increasing negative gate voltage. In addition, the effect of drift doping on breakdown voltage is discussed. The maximum breakdown voltage of approximately 11kV is achieved with drain leakage current of the order of 10-7 A. The novelty of proposed design verifies the improvement in breakdown voltage observed by the experimentally reported data.